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公开(公告)号：US10955472B1
公开(公告)日：2021-03-23
申请号：US16444917
申请日：2019-06-18
Applicant: Amazon Technologies, Inc.
Inventor： Dan Trock , Valentin Bader , Shlomi Vilozny , Shimon Rahamim , Danny Sapoznikov , Yair Armoza , Itai Avron
IPC: G01R31/3177 , G01R31/317
Abstract: An integrated circuit includes first and second cores. Each core has a power-switchable portion in a first power domain in which an operating power is turned on or off in response to a power control signal. The first power domain includes a first scan chain, and the first power domain also includes a plurality of outputs. Each core also includes an always-on portion in a second power domain in which the operating power is maintained during testing of the integrated circuit. The second power domain also has a second scan chain. The second power domain further includes respective isolation gates coupled to the plurality of outputs of the first power domain, and the second scan chain includes a respective wrapper cell coupled to some isolation gates. The integrated circuit is configured to power off and isolate the power-switchable portion in the first power domain based on a scan test result.
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Patent Agency Ranking
公开(公告)号：US10990739B1
公开(公告)日：2021-04-27
申请号：US16366717
申请日：2019-03-27
Applicant: Amazon Technologies, Inc.
Inventor： Dan Trock , Sergey Kleyman , Danny Sapoznikov
IPC: G06F30/392 , H01L23/498 , H01L23/00
Abstract: An integrated circuit device includes multiple circuit tiles disposed in a tiled arrangement in a circuit block between a first boundary and a second boundary. Each circuit tile is an instance of a circuit cell having a first edge and a second edge. The circuit cell has a scan channel circuit that includes a configurable scan channel switch and scan channels extending between the first edge and the second edge of the circuit cell through the configurable scan channel switch. Respective scan channels in the multiple circuit tiles are joined together and extend between the first boundary and the second boundary of the block of tiled arrangement. Each circuit tile can be configured to receive scan-in test data through a scan channel from either the first boundary or the second boundary, and to output scan-out result data of the circuit tile through a scan channel to either the first boundary or the second boundary.
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公开(公告)号：US09983262B1
公开(公告)日：2018-05-29
申请号：US15198217
申请日：2016-06-30
Applicant: AMAZON TECHNOLOGIES, INC.
Inventor： Dan Trock , Ron Diamant
IPC: G01R31/28 , G01R31/317 , G01R31/3187 , G01R31/3177 , G01R31/3185
CPC classification number: G01R31/31724 , G01R31/3177 , G01R31/318525 , G01R31/31853 , G01R31/3187
Abstract: A device includes one or more random number generator (RNG) cores (e.g., true random number generator cores) and a built-in self-test controller (BIST) configured to perform various fault tests on each RNG core. The tests include a stuck-at-1 fault test, a stuck-at-0 fault test, and a transition delay fault test. For those RNG cores that have multiple ring oscillators, each individual ring oscillator is fault tested by the BIST controller. For those RNG cores that have a multi-tap inverter chain configuration, the individual taps may be tested by the BIST controller. The RNG core also may comprise a bi-stable cell which can be tested by the BIST controller as well.
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公开(公告)号：US11567130B1
公开(公告)日：2023-01-31
申请号：US17247217
申请日：2020-12-03
Applicant: Amazon Technologies, Inc.
Inventor： Dan Trock , Alon Postavski , Etai Wagner , Victor David Romanov
IPC: G01R31/3177 , G01R31/317
Abstract: An integrated circuit device may include core circuitry, and a set of external interface buffer circuits coupled to the core circuitry. To improve test time and accuracy, as well as to simplify test procedures during voltage testing of the set of external interface buffer circuits, the integrated circuit device may include a test circuit and a combinational logic circuit coupled to the set of external interface buffer circuits. The combinational logic circuit is configured to combine a logic level of each of the external interface buffer circuits into a test signal, and the test circuit is configured to execute a voltage test on the set of external interface buffer circuits based on a logic level of the test signal.
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公开(公告)号：US10187044B1
公开(公告)日：2019-01-22
申请号：US15694165
申请日：2017-09-01
Applicant: AMAZON TECHNOLOGIES, INC.
Inventor： Ron Diamant , Dan Trock , Elad Valfer , Yair Armoza
Abstract: A bistable cell includes a pair of inverters and multiple pairs of cross-coupled tristate buffers. Each pair of tristate buffers can be individually selected to implement an entropy harvesting state for the bistable cell. Each of the tristate buffers generally has lower strength than the inverters but the inverter-to-buffer strength ratio can be configured through selective use of one or more of the tristate buffer pairs. The resulting entropy harvesting state behavior can be varied based on the inverter-to-buffer strength ratio in terms of greater randomness of the output bits or decreased power consumption.
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公开(公告)号：US09774317B1
公开(公告)日：2017-09-26
申请号：US15250574
申请日：2016-08-29
Applicant: AMAZON TECHNOLOGIES, INC.
Inventor： Ron Diamant , Dan Trock , Elad Valfer , Yair Armoza
CPC classification number: H03K3/84 , G06F7/588 , G06F13/4045 , H03K3/03 , H03K19/0002 , Y02D10/14 , Y02D10/151
Abstract: A bistable cell includes a pair of inverters and multiple pairs of cross-coupled tristate buffers. Each pair of tristate buffers can be individually selected to implement an entropy harvesting state for the bistable cell. Each of the tristate buffers generally has lower strength than the inverters but the inverter-to-buffer strength ratio can be configured through selective use of one or more of the tristate buffer pairs. The resulting entropy harvesting state behavior can be varied based on the inverter-to-buffer strength ratio in terms of greater randomness of the output bits or decreased power consumption.
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