公开(公告)号：US20070186200A1

公开(公告)日：2007-08-09

申请号：US11350667

申请日：2006-02-08

申请人： Amir Farrahi ,  Anurag Bhatnagar ,  Nabanjan Das

发明人： Amir Farrahi ,  Anurag Bhatnagar ,  Nabanjan Das

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： One embodiment of the present invention provides a system that determines a feasible cell placement for an integrated circuit design. During operation, the system receives an input cell placement, which is typically determined using a quadratic placement technique. Next, the system receives a set of regions within the integrated circuit design. Each region has a capacity constraint which specifies an upper limit on the total cell area that can be placed within the region. The system then generates a bi-partite graph which comprises instance vertices, region vertices, and edges. An instance vertex is associated with a cell instance, a region vertex is associated with a region, and each edge is incident on an instance vertex and a region vertex. Each edge is assigned a cost that indicates the cost of placing the associated cell instance in the associated region. Next, the system associates edges with shadow edges. Note that an edge and an associated shadow edge are incident to the same instance vertex. The system then ranks the edges using the costs of the shadow edges. Next, the system selects a set of edges using the edge rankings. Finally, the system determines the feasible cell placement using the set of edges.

摘要翻译： 本发明的一个实施例提供一种确定用于集成电路设计的可行单元布局的系统。 在操作期间，系统接收输入单元布置，其通常使用二次放置技术来确定。 接下来，系统在集成电路设计中接收一组区域。 每个区域具有容量约束，其规定可以放置在该区域内的总单元格区域的上限。 然后，系统生成包括实例顶点，区域顶点和边缘的双分图。 实例顶点与单元格实例相关联，区域顶点与区域相关联，每个边缘都入射到实例顶点和区域顶点。 为每个边缘分配一个成本，指示将关联的单元格实例放置在关联区域中的成本。 接下来，系统将边缘与阴影边缘相关联。 请注意，边缘和相关联的阴影边缘入射到相同的实例顶点。 然后系统使用阴影边缘的成本对边缘进行排序。 接下来，系统使用边缘排序来选择一组边。 最后，系统使用该组边确定可行的单元布局。

公开(公告)号：US20060038602A1

公开(公告)日：2006-02-23

申请号：US11255707

申请日：2005-10-21

申请人： Anthony Bonaccio ,  John Cohn ,  Alvar Dean ,  Amir Farrahi ,  David Hathaway ,  Sebastian Ventrone

发明人： Anthony Bonaccio ,  John Cohn ,  Alvar Dean ,  Amir Farrahi ,  David Hathaway ,  Sebastian Ventrone

IPC分类号： G06F1/04

CPC分类号： G06F1/10

摘要： A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and convert the differential sinusoidal pair to local clock signals. Power consumption and noise generation are reduced as compared to conventional clock signal distribution arrangements.

公开(公告)号：US20050262463A1

公开(公告)日：2005-11-24

申请号：US11176712

申请日：2005-07-07

申请人： John Cohn ,  Alvar Dean ,  Amir Farrahi ,  David Hathaway ,  Thomas Lepsic ,  Jagannathan Narasimhan ,  Scott Tetreault ,  Sebastian Ventrone

发明人： John Cohn ,  Alvar Dean ,  Amir Farrahi ,  David Hathaway ,  Thomas Lepsic ,  Jagannathan Narasimhan ,  Scott Tetreault ,  Sebastian Ventrone

IPC分类号： G06F17/50 ,  H01L21/82 ,  G06F9/45 ,  H03K19/0175

CPC分类号： G06F17/5072 ,  G06F17/5022 ,  G06F17/5077

摘要： An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.

摘要翻译： 电气布线结构及其设计方法。 该方法识别具有第一线和第二线的至少一个线对。 第二根线已经是三态的，也可以是三态的。 线对可以具有不小于预定或用户选择的最小相同方向切换概率的每时钟周期的相同方向的切换概率。 或者，线对可以具有不小于预定或用户选择的最小相反方向切换概率的每时钟周期的相反方向切换概率。 第一线和第二线满足至少一个数学关系，涉及：第一线和第二线之间的间隔; 以及第一线和第二线的公共行程长度。

公开(公告)号：US20080074147A1

公开(公告)日：2008-03-27

申请号：US11952544

申请日：2007-12-07

申请人： John Cohn ,  Alvar Dean ,  Amir Farrahi ,  David Hathaway ,  Thomas Lepsic ,  Jagannathan Narasimhan ,  Scott Tetreault ,  Sebastian Ventrone

发明人： John Cohn ,  Alvar Dean ,  Amir Farrahi ,  David Hathaway ,  Thomas Lepsic ,  Jagannathan Narasimhan ,  Scott Tetreault ,  Sebastian Ventrone

IPC分类号： H03K19/00 ,  G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5022 ,  G06F17/5077

摘要： An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability φSD per clock cycle that is no less than a pre-selected minimum same-direction switching probability φSD,MIN or has an opposite-direction switching probability φOD per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability φOD,MIN. The first wire and the second wire satisfies at least one mathematical relationship involving LCOMMON and WSPACING, where WSPACING is defined as a spacing between the first wire and the second wire, and LCOMMON is defined as a common run length of the first wire and the second wire.

摘要翻译： 一种用于设计电气布线结构的电气布线结构和计算机系统。 电气配线结构包括电线对。 线对包括第一线和第二线。 第二根电线被预定为三态。 线对具有不小于预先选择的最小相同方向切换概率phi，SD，MIN或/或具有相同方向的切换概率，每时钟周期 每个时钟周期的相反方向切换概率Φ不小于预先选择的最小相对方向切换概率φi，MIN 。 第一线和第二线满足至少一个数学关系，其涉及公平和平坦，其中，W SPACING 被定义为 第一线和第二线，以及公共被定义为第一线和第二线的公共行程长度。

公开(公告)号：US06611945B1

公开(公告)日：2003-08-26

申请号：US09696718

申请日：2000-10-25

申请人： Jagannathan Narasimhan ,  Amir Farrahi

发明人： Jagannathan Narasimhan ,  Amir Farrahi

IPC分类号： G06F1750

CPC分类号： G06F17/5022 ,  G06F2217/10 ,  G06F2217/78

摘要： A method is provided for computing signal and switching probabilities at an output of a logic circuit in a network having multiple logic circuits. The method for computing the signal and switching probabilities includes steps of creating a truth table for a logic circuit where the truth table has entries respectively corresponding to signals at inputs of the logic circuit, choosing in sequence one of entries each representing switching of a signal at the output of the circuit, determining whether a signal at an input corresponding to the chosen entry is at logic high, assigning an event probability representing that the signal is at logic high, and accumulating event probabilities respectively assigned to signals at inputs corresponding to the chosen entries to produce the signal probability at the output of the circuit.

摘要翻译： 提供一种用于在具有多个逻辑电路的网络中的逻辑电路的输出处计算信号和切换概率的方法。 用于计算信号和切换概率的方法包括以下步骤：为逻辑电路创建真值表，其中真值表具有分别对应于逻辑电路的输入处的信号的条目，顺序地选择一个表示在 电路的输出，确定与所选择的条目相对应的输入处的信号是否处于逻辑高电平，分配表示该信号处于逻辑高电平的事件概率，以及分别分配给与所选择的输入相对应的输入端的信号的事件概率 条目在电路的输出端产生信号概率。