公开(公告)号：US07370305B2

公开(公告)日：2008-05-06

申请号：US11350667

申请日：2006-02-08

申请人： Amir H. Farrahi ,  Anurag Bhatnagar ,  Nabanjan Das

发明人： Amir H. Farrahi ,  Anurag Bhatnagar ,  Nabanjan Das

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： One embodiment of the present invention provides a system that determines a feasible cell placement for an integrated circuit design. During operation, the system receives an input cell placement, which is typically determined using a quadratic placement technique. Next, the system receives a set of regions within the integrated circuit design. Each region has a capacity constraint which specifies an upper limit on the total cell area that can be placed within the region. The system then generates a bi-partite graph which comprises instance vertices, region vertices, and edges. An instance vertex is associated with a cell instance, a region vertex is associated with a region, and each edge is incident on an instance vertex and a region vertex. Each edge is assigned a cost that indicates the cost of placing the associated cell instance in the associated region. Next, the system associates edges with shadow edges. Note that an edge and an associated shadow edge are incident to the same instance vertex. The system then ranks the edges using the costs of the shadow edges. Next, the system selects a set of edges using the edge rankings. Finally, the system determines the feasible cell placement using the set of edges.

摘要翻译： 本发明的一个实施例提供一种确定用于集成电路设计的可行单元布局的系统。 在操作期间，系统接收输入单元布置，其通常使用二次放置技术来确定。 接下来，系统在集成电路设计中接收一组区域。 每个区域具有容量约束，其规定可以放置在该区域内的总单元格区域的上限。 然后，系统生成包括实例顶点，区域顶点和边缘的双分图。 实例顶点与单元格实例相关联，区域顶点与区域相关联，每个边缘都入射到实例顶点和区域顶点。 为每个边缘分配一个成本，指示将关联的单元格实例放置在关联区域中的成本。 接下来，系统将边缘与阴影边缘相关联。 请注意，边缘和相关联的阴影边缘入射到相同的实例顶点。 然后系统使用阴影边缘的成本对边缘进行排序。 接下来，系统使用边缘排序来选择一组边。 最后，系统使用该组边确定可行的单元布局。

公开(公告)号：US20070186200A1

公开(公告)日：2007-08-09

申请号：US11350667

申请日：2006-02-08

申请人： Amir Farrahi ,  Anurag Bhatnagar ,  Nabanjan Das

发明人： Amir Farrahi ,  Anurag Bhatnagar ,  Nabanjan Das

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： One embodiment of the present invention provides a system that determines a feasible cell placement for an integrated circuit design. During operation, the system receives an input cell placement, which is typically determined using a quadratic placement technique. Next, the system receives a set of regions within the integrated circuit design. Each region has a capacity constraint which specifies an upper limit on the total cell area that can be placed within the region. The system then generates a bi-partite graph which comprises instance vertices, region vertices, and edges. An instance vertex is associated with a cell instance, a region vertex is associated with a region, and each edge is incident on an instance vertex and a region vertex. Each edge is assigned a cost that indicates the cost of placing the associated cell instance in the associated region. Next, the system associates edges with shadow edges. Note that an edge and an associated shadow edge are incident to the same instance vertex. The system then ranks the edges using the costs of the shadow edges. Next, the system selects a set of edges using the edge rankings. Finally, the system determines the feasible cell placement using the set of edges.

摘要翻译： 本发明的一个实施例提供一种确定用于集成电路设计的可行单元布局的系统。 在操作期间，系统接收输入单元布置，其通常使用二次放置技术来确定。 接下来，系统在集成电路设计中接收一组区域。 每个区域具有容量约束，其规定可以放置在该区域内的总单元格区域的上限。 然后，系统生成包括实例顶点，区域顶点和边缘的双分图。 实例顶点与单元格实例相关联，区域顶点与区域相关联，每个边缘都入射到实例顶点和区域顶点。 为每个边缘分配一个成本，指示将关联的单元格实例放置在关联区域中的成本。 接下来，系统将边缘与阴影边缘相关联。 请注意，边缘和相关联的阴影边缘入射到相同的实例顶点。 然后系统使用阴影边缘的成本对边缘进行排序。 接下来，系统使用边缘排序来选择一组边。 最后，系统使用该组边确定可行的单元布局。