公开(公告)号：US08130939B2

公开(公告)日：2012-03-06

申请号：US11731232

申请日：2007-03-30

申请人： Amir Mezer ,  Adee Ran ,  Ehud Shoor ,  Harry Birenboim ,  Yaniv Hadar ,  Assaf Benhamou

发明人： Amir Mezer ,  Adee Ran ,  Ehud Shoor ,  Harry Birenboim ,  Yaniv Hadar ,  Assaf Benhamou

IPC分类号： H04M9/00

CPC分类号： H04B3/235 ,  H04B3/52

摘要： In one embodiment, the present invention includes an apparatus having an automatic gain control (AGC) stage to receive an input signal from a communication channel physical medium, a first local gain stage coupled to an output of the AGC stage, an equalizer coupled to an output of the first local gain stage, an echo canceller to receive local data to be transmitted along the communication channel physical medium, and a second local gain stage coupled to an output of the echo canceller. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括具有自动增益控制（AGC）级的装置，用于从通信信道物理介质接收输入信号，耦合到AGC级的输出的第一局部增益级，耦合到 第一本地增益级的输出，用于接收沿着通信信道物理介质发送的本地数据的回波消除器，以及耦合到回声消除器的输出的第二局部增益级。 描述和要求保护其他实施例。

公开(公告)号：US08175823B2

公开(公告)日：2012-05-08

申请号：US12316900

申请日：2008-12-17

申请人： Amir Mezer ,  Assaf Benhamou

发明人： Amir Mezer ,  Assaf Benhamou

IPC分类号： H03K5/153

CPC分类号： G01R31/3163 ,  G01R31/31715

摘要： A device, comprising a monitoring slicer adapted to repeatedly sample an internal analog signal to provide a sequence of digital outputs indicating a result of a comparison of the level of the internal analog signal to a reference voltage and an operative unit adapted to perform a task of the device and provide a result without using digital outputs from the monitoring slicer.

摘要翻译： 一种装置，包括监视限幅器，适于反复取样内部模拟信号，以提供指示内部模拟信号的电平与参考电压的比较结果的数字输出序列，以及适于执行任务的操作单元 该设备并提供结果，而不使用来自监控限幅器的数字输出。

公开(公告)号：US20100153032A1

公开(公告)日：2010-06-17

申请号：US12316900

申请日：2008-12-17

申请人： Amir Mezer ,  Assaf Benhamou

发明人： Amir Mezer ,  Assaf Benhamou

IPC分类号： G01R15/00 ,  H03K5/153

CPC分类号： G01R31/3163 ,  G01R31/31715

摘要： A device, comprising a monitoring slicer adapted to repeatedly sample an internal analog signal to provide a sequence of digital outputs indicating a result of a comparison of the level of the internal analog signal to a reference voltage and an operative unit adapted to perform a task of the device and provide a result without using digital outputs from the monitoring slicer.

摘要翻译： 一种装置，包括监视限幅器，适于反复取样内部模拟信号，以提供指示内部模拟信号的电平与参考电压的比较结果的数字输出序列，以及适于执行任务的操作单元 该设备并提供结果，而不使用来自监控限幅器的数字输出。

公开(公告)号：US20080240412A1

公开(公告)日：2008-10-02

申请号：US11731232

申请日：2007-03-30

申请人： Amir Mezer ,  Adee Ran ,  Ehud Shoor ,  Harry Birenboim ,  Yaniv Hadar ,  Assaf Benhamou

发明人： Amir Mezer ,  Adee Ran ,  Ehud Shoor ,  Harry Birenboim ,  Yaniv Hadar ,  Assaf Benhamou

IPC分类号： H04M9/08

CPC分类号： H04B3/235 ,  H04B3/52

摘要： In one embodiment, the present invention includes an apparatus having an automatic gain control (AGC) stage to receive an input signal from a communication channel physical medium, a first local gain stage coupled to an output of the AGC stage, an equalizer coupled to an output of the first local gain stage, an echo canceler to receive local data to be transmitted along the communication channel physical medium, and a second local gain stage coupled to an output of the echo canceler. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括具有自动增益控制（AGC）级的装置，用于从通信信道物理介质接收输入信号，耦合到AGC级的输出的第一局部增益级，耦合到 第一本地增益级的输出，回波消除器，用于接收沿着通信信道物理介质发送的本地数据，以及耦合到回波消除器的输出的第二局部增益级。 描述和要求保护其他实施例。

公开(公告)号：US20120154185A1

公开(公告)日：2012-06-21

申请号：US12969249

申请日：2010-12-15

申请人： Ehud Shoor ,  Dror Lazar ,  Assaf Benhamou

发明人： Ehud Shoor ,  Dror Lazar ,  Assaf Benhamou

IPC分类号： H03M9/00

CPC分类号： H03M9/00 ,  H04J3/0608

摘要： In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括解串器，用于以第一速率接收串行数据，并响应于从反馈回路接收到的相位控制信号，输出对应于与帧对准边界对准的串行数据的并行数据帧 耦合在解串器和耦合到解串器的输出的接收器逻辑之间。 描述和要求保护其他实施例。

公开(公告)号：US20160182175A1

公开(公告)日：2016-06-23

申请号：US14574482

申请日：2014-12-18

申请人： Yoni Landau ,  Assaf Benhamou ,  Adee O. Ran

发明人： Yoni Landau ,  Assaf Benhamou ,  Adee O. Ran

IPC分类号： H04J3/06 ,  H04L7/04

CPC分类号： H04J3/0658 ,  H04L7/041 ,  H04L12/12 ,  H04L2007/045 ,  Y02D50/40 ,  Y02D50/42

摘要： Technologies for robust data transmission include a network port logic having a physical coding sublayer (PCS). The PCS may transmit a series of rapid alignment markers (RAMs) to a link partner, with each RAM indicative of a counter value. The PCS transitions to a sleep state if the counter value equals two and a low power idle (LPI) command is set by an upper-layer client. The PCS transitions to an active state if the counter value equals one and the LPI command is not set. The PCS may receive a low power idle symbol (LI) from the link partner and start a guard timer in response to receipt of the LI symbol. The PCS transitions to a sleep state if the guard timer expires and transitions to the active state if data other than LI is received prior to expiration of the guard timer. Other embodiments are described and claimed.

摘要翻译： 用于鲁棒数据传输的技术包括具有物理编码子层（PCS）的网络端口逻辑。 PCS可以将一系列快速对准标记（RAM）发送到链路伙伴，每个RAM指示计数器值。 如果计数器值等于2，并且上层客户端设置了低功耗空闲（LPI）命令，则PCS转换到睡眠状态。 如果计数器值等于1并且未设置LPI命令，则PCS将转换到活动状态。 PCS可以从链路伙伴接收低功率空闲符号（LI），并且响应于LI符号的接收而启动保护定时器。 如果保护定时器到期，则PCS转换到睡眠状态，并且如果在保护定时器到期之前接收到除L1之外的数据，则转换到活动状态。 描述和要求保护其他实施例。

公开(公告)号：US08405533B2

公开(公告)日：2013-03-26

申请号：US12969249

申请日：2010-12-15

申请人： Ehud Shoor ,  Dror Lazar ,  Assaf Benhamou

发明人： Ehud Shoor ,  Dror Lazar ,  Assaf Benhamou

IPC分类号： H03M9/00

CPC分类号： H03M9/00 ,  H04J3/0608

摘要： In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括解串器，用于以第一速率接收串行数据，并且响应于从反馈回路接收的相位控制信号，输出与对准边界对准的串行数据的并行数据帧 耦合在解串器和耦合到解串器的输出的接收器逻辑之间。 描述和要求保护其他实施例。

公开(公告)号：US08314724B2

公开(公告)日：2012-11-20

申请号：US12969249

申请日：2010-12-15

申请人： Ehud Shoor ,  Dror Lazar ,  Assaf Benhamou

发明人： Ehud Shoor ,  Dror Lazar ,  Assaf Benhamou

IPC分类号： H03M9/00

摘要： In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.