公开(公告)号：US08805917B2

公开(公告)日：2014-08-12

申请号：US13177491

申请日：2011-07-06

申请人： Amira Mohamed ,  Ramy Raafat ,  Hossam Ali Hassan Fahmy ,  Tarek Eldeeb ,  Yasmeen Farouk ,  Rodina Samy ,  Mostafa Elkhouly

发明人： Amira Mohamed ,  Ramy Raafat ,  Hossam Ali Hassan Fahmy ,  Tarek Eldeeb ,  Yasmeen Farouk ,  Rodina Samy ,  Mostafa Elkhouly

IPC分类号： G06F7/48

CPC分类号： G06F7/492 ,  G06F7/483 ,  G06F7/5336 ,  G06F7/5443 ,  G06F2207/5355

摘要： A circuit for performing a floating-point fused-multiply-add (FMA) calculation of a×b±c. The circuit includes (i) a partial product generation module having (a) a multiples generator unit configured to generate multiples of a multiplicand has m digit binary coded decimal (BCD) format, (b) a recoding unit configured to generate n+1 signed digits (SD) sets from a sum vector and a carry vector of a multiplier, and (c) a multiples selection unit configured to generate partial product vectors from the multiples of the multiplicand based on the n+1 SD sets and the sign of FMA calculation, and (ii) a carry save adder (CSA) tree configured to add the partial product vectors and an addend to generate a result sum vector and a result carry vector in a m+n digit BCD format.

摘要翻译： 用于执行×b±c的浮点融合乘法（FMA）计算的电路。 电路包括（i）部分乘积生成模块，其具有（a）多个发生器单元，被配置为生成具有m位二进制编码十进制（BCD）格式的被乘数的倍数，（b）被配置为生成n + 1个符号的重新编码单元 数字（SD）从乘法器的和向量和进位向量设置，以及（c）多个选择单元，被配置为基于n + 1个SD集合和FMA的符号从被乘数的倍数生成部分乘积向量 计算，以及（ii）进位保存加法器（CSA）树，其被配置为添加部分乘积向量和加数以生成m + n位BCD格式的结果和矢量和结果进位向量。

公开(公告)号：US20120011182A1

公开(公告)日：2012-01-12

申请号：US13177488

申请日：2011-07-06

申请人： Ramy Raafat ,  Amira Mohamed ,  Hossam Ali Hassan Fahmy ,  Yasmeen Farouk ,  Mostafa Elkhouly ,  Tarek Eldeeb ,  Rodina Samy

发明人： Ramy Raafat ,  Amira Mohamed ,  Hossam Ali Hassan Fahmy ,  Yasmeen Farouk ,  Mostafa Elkhouly ,  Tarek Eldeeb ,  Rodina Samy

IPC分类号： G06F7/552 ,  G06F5/01

CPC分类号： G06F7/5525 ,  G06F7/491 ,  G06F2207/5355

摘要： A system including: an input processing unit configured to: extract a significant and a bias exponent from the decimal floating-point radicand; and calculate a normalized significand; a square root unit configured to: calculate, using a FMA unit, a refined reciprocal square-root of the normalized significand; calculate an unrounded square-root of the normalized significand by multiplying the refined reciprocal square-root by the normalized significand; and generate a rounded square-root based on a first difference between the normalized significand and a square of the unrounded square-root; a master control unit operatively connected to the input processing hardware unit and the square-root hardware unit and configured to calculate an exponent for the unrounded square-root based on the number of leading zeros and a precision of the decimal floating-point radicand; and an output formulation unit configured to output a decimal floating-point square-root of the radicand based on the rounded square-root and the exponent.

摘要翻译： 一种系统，包括：输入处理单元，被配置为：从十进制浮点radic中提取有效偏移指数和偏差指数; 并计算归一化有效位数; 平方根单元，其被配置为：使用FMA单元计算所述归一化有效位数的精确相互平方根; 通过将精确的倒数平方根乘以归一化有效位数来计算标准化有效位数的未圆角平方根; 并且基于归一化有效位数和未包围的平方根的平方之间的第一差异生成舍入的平方根; 主控制单元，可操作地连接到输入处理硬件单元和平方根硬件单元，并且被配置为基于前导零的数量和十进制浮点数的精度来计算未包围的平方根的指数; 以及输出公式单元，被配置为基于所述舍入的平方根和所述指数输出所述radic的十进制浮点平方根。

公开(公告)号：US20120011187A1

公开(公告)日：2012-01-12

申请号：US13177491

申请日：2011-07-06

申请人： Amira Mohamed ,  Ramy Raafat ,  Hossam Ali Hassan Fahmy ,  Tarek Eldeeb ,  Yasmeen Farouk ,  Rodina Samy ,  Mostafa Elkhouly

发明人： Amira Mohamed ,  Ramy Raafat ,  Hossam Ali Hassan Fahmy ,  Tarek Eldeeb ,  Yasmeen Farouk ,  Rodina Samy ,  Mostafa Elkhouly

IPC分类号： G06F7/52 ,  G06F7/50

CPC分类号： G06F7/492 ,  G06F7/483 ,  G06F7/5336 ,  G06F7/5443 ,  G06F2207/5355

摘要： A circuit for performing a floating-point fused-multiply-add (FMA) calculation of a×b±c. The circuit includes (i) a partial product generation module having (a) a multiples generator unit configured to generate multiples of a multiplicand has m digit binary coded decimal (BCD) format, (b) a recoding unit configured to generate n+1 signed digits (SD) sets from a sum vector and a carry vector of a multiplier, and (c) a multiples selection unit configured to generate partial product vectors from the multiples of the multiplicand based on the n+1 SD sets and the sign of FMA calculation, and (ii) a carry save adder (CSA) tree configured to add the partial product vectors and an addend to generate a result sum vector and a result carry vector in a m+n digit BCD format.

摘要翻译： 用于执行×b±c的浮点融合乘法（FMA）计算的电路。 电路包括（i）部分乘积生成模块，其具有（a）多个发生器单元，被配置为生成具有m位二进制编码十进制（BCD）格式的被乘数的倍数，（b）被配置为生成n + 1个符号的重新编码单元 数字（SD）从乘法器的和向量和进位向量设置，以及（c）多个选择单元，被配置为基于n + 1个SD集合和FMA的符号从被乘数的倍数生成部分乘积向量 计算，以及（ii）进位保存加法器（CSA）树，其被配置为添加部分乘积向量和加数以生成m + n位BCD格式的结果和矢量和结果进位向量。

公开(公告)号：US20120011181A1

公开(公告)日：2012-01-12

申请号：US13177549

申请日：2011-07-06

申请人： Rodina Samy ,  Hossam Ali Hassan Fahmy ,  Tarek Eldeeb ,  Ramy Raafat ,  Yasmeen Farouk ,  Mostafa Elkhouly ,  Amira Mohamed

发明人： Rodina Samy ,  Hossam Ali Hassan Fahmy ,  Tarek Eldeeb ,  Ramy Raafat ,  Yasmeen Farouk ,  Mostafa Elkhouly ,  Amira Mohamed

IPC分类号： G06F7/487 ,  G06F7/499 ,  G06F7/485

CPC分类号： G06F7/483 ,  G06F7/491 ,  G06F7/5443

摘要： A decimal floating-point Fused-Multiply-Add (FMA) unit that performs the operation of ±(A×B)±C on decimal floating-point operands. The decimal floating-point FMA unit executes the multiplication and addition operations compliant with the IEEE 754-2008 standard. Specifically, the decimal floating-point FMA includes a parallel multiplier and injects the addend after required alignment as an additional partial product in the reduction tree used in the parallel multiplier. The decimal floating-point FMA unit may be configured to perform addition-subtraction operations or multiplication operations as standalone operations.

摘要翻译： 在十进制浮点运算符上执行±（A×B）±C的运算的十进制浮点Fused-Multiply-Add（FMA）单位。 十进制浮点FMA单元执行符合IEEE 754-2008标准的乘法和加法运算。 具体来说，十进制浮点FMA包括一个并行乘法器，并将所需对齐后的加数作为并行乘法器中使用的还原树中的附加部分乘积进行注入。 十进制浮点FMA单元可以被配置为执行加减运算或乘法运算作为独立运算。

公开(公告)号：US08812575B2

公开(公告)日：2014-08-19

申请号：US13177488

申请日：2011-07-06

申请人： Ramy Raafat ,  Amira Mohamed ,  Hossam Ali Hassan Fahmy ,  Yasmeen Farouk ,  Mostafa Elkhouly ,  Tarek Eldeeb ,  Rodina Samy

发明人： Ramy Raafat ,  Amira Mohamed ,  Hossam Ali Hassan Fahmy ,  Yasmeen Farouk ,  Mostafa Elkhouly ,  Tarek Eldeeb ,  Rodina Samy

IPC分类号： G06F7/552

CPC分类号： G06F7/5525 ,  G06F7/491 ,  G06F2207/5355

摘要： A system including: an input processing unit configured to: extract a significant and a bias exponent from the decimal floating-point radicand; and calculate a normalized significand; a square root unit configured to: calculate, using a FMA unit, a refined reciprocal square-root of the normalized significand; calculate an unrounded square-root of the normalized significand by multiplying the refined reciprocal square-root by the normalized significand; and generate a rounded square-root based on a first difference between the normalized significand and a square of the unrounded square-root; a master control unit operatively connected to the input processing hardware unit and the square-root hardware unit and configured to calculate an exponent for the unrounded square-root based on the number of leading zeros and a precision of the decimal floating-point radicand; and an output formulation unit configured to output a decimal floating-point square-root of the radicand based on the rounded square-root and the exponent.

摘要翻译： 一种系统，包括：输入处理单元，被配置为：从十进制浮点radic中提取有效偏移指数和偏差指数; 并计算归一化有效位数; 平方根单元，其被配置为：使用FMA单元计算所述归一化有效位数的精确相互平方根; 通过将精确的倒数平方根乘以归一化有效位数来计算标准化有效位数的未圆角平方根; 并且基于归一化有效位数和未包围的平方根的平方之间的第一差异生成舍入的平方根; 主控制单元，可操作地连接到输入处理硬件单元和平方根硬件单元，并且被配置为基于前导零的数量和十进制浮点数的精度来计算未包围的平方根的指数; 以及输出公式单元，被配置为基于所述舍入的平方根和所述指数输出所述radic的十进制浮点平方根。

公开(公告)号：US08751555B2

公开(公告)日：2014-06-10

申请号：US13177484

申请日：2011-07-06

申请人： Amira Mohamed ,  Hossam Ali Hassan Fahmy ,  Ramy Raafat ,  Yasmeen Farouk ,  Mostafa Elkhouly ,  Rodina Samy ,  Tarek Eldeeb

发明人： Amira Mohamed ,  Hossam Ali Hassan Fahmy ,  Ramy Raafat ,  Yasmeen Farouk ,  Mostafa Elkhouly ,  Rodina Samy ,  Tarek Eldeeb

IPC分类号： G06F7/38

CPC分类号： G06F7/49957 ,  G06F7/4917 ,  G06F2207/5355 ,  G06F2207/5356

摘要： A method for performing a decimal floating-point division, including: receiving, by a decimal floating-point divider, a decimal floating-point dividend and a decimal floating-point divisor; obtaining, by the decimal floating-point divider, a preliminary quotient having a first precision level, where the preliminary quotient is calculated from the decimal floating-point dividend and the decimal-floating point divisor; receiving, by the decimal floating-point divider, a rounding mode; selecting a rounding action based on the preliminary quotient and the rounding mode; and obtaining a rounded quotient having a second precision level by rounding the preliminary quotient according to the rounding action, where the first precision level is at least one digit greater than the second precision level.

摘要翻译： 一种用于执行十进制浮点除法的方法，包括：由十进制浮点除法器接收十进制浮点除数和十进制浮点除数; 通过十进制浮点除法器获得具有第一精度水平的初级商，其中从十进制浮点除数和十进制浮点除数计算初步商; 通过十进制浮点分频器接收舍入模式; 基于初步商和舍入模式选择舍入动作; 以及通过根据所述舍入动作舍入所述初级商，获得具有第二精度等级的舍入商，其中所述第一精度级别比所述第二精度级别大至少一位数。

公开(公告)号：US08694572B2

公开(公告)日：2014-04-08

申请号：US13177549

申请日：2011-07-06

申请人： Rodina Samy ,  Hossam Ali Hassan Fahmy ,  Tarek Eldeeb ,  Ramy Raafat ,  Yasmeen Farouk ,  Mostafa Elkhouly ,  Amira Mohamed

发明人： Rodina Samy ,  Hossam Ali Hassan Fahmy ,  Tarek Eldeeb ,  Ramy Raafat ,  Yasmeen Farouk ,  Mostafa Elkhouly ,  Amira Mohamed

IPC分类号： G06F7/38

CPC分类号： G06F7/483 ,  G06F7/491 ,  G06F7/5443

摘要： A decimal floating-point Fused-Multiply-Add (FMA) unit that performs the operation of ±(A×B)±C on decimal floating-point operands. The decimal floating-point FMA unit executes the multiplication and addition operations compliant with the IEEE 754-2008 standard. Specifically, the decimal floating-point FMA includes a parallel multiplier and injects the addend after required alignment as an additional partial product in the reduction tree used in the parallel multiplier. The decimal floating-point FMA unit may be configured to perform addition-subtraction operations or multiplication operations as standalone operations.

摘要翻译： 在十进制浮点运算符上执行±（A×B）±C的运算的十进制浮点Fused-Multiply-Add（FMA）单位。 十进制浮点FMA单元执行符合IEEE 754-2008标准的乘法和加法运算。 具体来说，十进制浮点FMA包括一个并行乘法器，并将所需对齐后的加数作为并行乘法器中使用的还原树中的附加部分乘积进行注入。 十进制浮点FMA单元可以被配置为执行加减运算或乘法运算作为独立运算。

公开(公告)号：US20120011185A1

公开(公告)日：2012-01-12

申请号：US13177484

申请日：2011-07-06

申请人： Amira Mohamed ,  Hossam Ali Hassan Fahmy ,  Ramy Raafat ,  Yasmeen Farouk ,  Mostafa Elkhouly ,  Rodina Samy ,  Tarek Eldeeb

发明人： Amira Mohamed ,  Hossam Ali Hassan Fahmy ,  Ramy Raafat ,  Yasmeen Farouk ,  Mostafa Elkhouly ,  Rodina Samy ,  Tarek Eldeeb

IPC分类号： G06F7/487

CPC分类号： G06F7/49957 ,  G06F7/4917 ,  G06F2207/5355 ,  G06F2207/5356

摘要： A method for performing a decimal floating-point division, including: receiving, by a decimal floating-point divider, a decimal floating-point dividend and a decimal floating-point divisor; obtaining, by the decimal floating-point divider, a preliminary quotient having a first precision level, where the preliminary quotient is calculated from the decimal floating-point dividend and the decimal-floating point divisor; receiving, by the decimal floating-point divider, a rounding mode; selecting a rounding action based on the preliminary quotient and the rounding mode; and obtaining a rounded quotient having a second precision level by rounding the preliminary quotient according to the rounding action, where the first precision level is at least one digit greater than the second precision level.

摘要翻译： 一种用于执行十进制浮点除法的方法，包括：由十进制浮点除法器接收十进制浮点除数和十进制浮点除数; 通过十进制浮点除法器获得具有第一精度水平的初级商，其中从十进制浮点除数和十进制浮点除数计算初步商; 通过十进制浮点分频器接收舍入模式; 基于初步商和舍入模式选择舍入动作; 以及通过根据所述舍入动作舍入所述初级商，获得具有第二精度等级的舍入商，其中所述第一精度级别比所述第二精度级别大至少一位数。