公开(公告)号：US08943457B2

公开(公告)日：2015-01-27

申请号：US12277285

申请日：2008-11-24

申请人： Amit Dinesh Sanghani ,  Punit Kishore

发明人： Amit Dinesh Sanghani ,  Punit Kishore

IPC分类号： G06F17/50 ,  G01R31/3185

CPC分类号： G01R31/318583

摘要： An aspect of the present invention replaces memory elements in a scan chain with corresponding new (memory) elements, with each new element having two paths to provide the corresponding data output. One of the two paths is operable to connect the data value to the combinational logic only during a capture phase of said test mode, and the second path is operable to connect the data value to the next element in the chain during a shift phase of said test mode. As a result, unneeded transitions/evaluations in the combinational logic are avoided during shift time, thereby reducing the resource requirements in the corresponding duration. However, the further processes (including various design phases and fabrication) are continued based on the original data (i.e., without the new elements) such that unneeded delays are avoided during the eventual operation in functional mode of the various fabricated IC units.

摘要翻译： 本发明的一个方面用相应的新（存储器）元件代替扫描链中的存储器元件，每个新元件具有两条路径以提供对应的数据输出。 两个路径中的一个可操作用于仅在所述测试模式的捕获阶段期间将数据值连接到组合逻辑，并且第二路径可操作以在所述测试模式的转换阶段期间将数据值连接到链中的下一个元素 测试模式。 结果，在移动时间期间避免了组合逻辑中的不必要的转换/评估，从而减少了相应持续时间内的资源需求。 然而，基于原始数据（即，没有新元件）继续进一步的处理（包括各种设计阶段和制造），使得在各种制造的IC单元的功能模式的最终操作期间避免不必要的延迟。

公开(公告)号：US20100131910A1

公开(公告)日：2010-05-27

申请号：US12277285

申请日：2008-11-24

申请人： Amit Dinesh Sanghani ,  Punit Kishore

发明人： Amit Dinesh Sanghani ,  Punit Kishore

IPC分类号： G06F17/50

CPC分类号： G01R31/318583

摘要： An aspect of the present invention replaces memory elements in a scan chain with corresponding new (memory) elements, with each new element having two paths to provide the corresponding data output. One of the two paths is operable to connect the data value to the combinational logic only during a capture phase of said test mode, and the second path is operable to connect the data value to the next element in the chain during a shift phase of said test mode. As a result, unneeded transitions/evaluations in the combinational logic are avoided during shift time, thereby reducing the resource requirements in the corresponding duration. However, the further processes (including various design phases and fabrication) are continued based on the original data (i.e., without the new elements) such that unneeded delays are avoided during the eventual operation in functional mode of the various fabricated IC units.

摘要翻译： 本发明的一个方面用相应的新（存储器）元件代替扫描链中的存储器元件，每个新元件具有两条路径以提供对应的数据输出。 两个路径中的一个可操作用于仅在所述测试模式的捕获阶段期间将数据值连接到组合逻辑，并且第二路径可操作以在所述测试模式的转换阶段期间将数据值连接到链中的下一个元素 测试模式。 结果，在移动时间期间避免了组合逻辑中的不必要的转换/评估，从而减少了相应持续时间内的资源需求。 然而，基于原始数据（即，没有新元件）继续进一步的处理（包括各种设计阶段和制造），使得在各种制造的IC单元的功能模式的最终操作期间避免不必要的延迟。

公开(公告)号：US06816991B2

公开(公告)日：2004-11-09

申请号：US09996866

申请日：2001-11-27

申请人： Amit Dinesh Sanghani

发明人： Amit Dinesh Sanghani

IPC分类号： G01R3128

CPC分类号： G11C7/106 ,  G01R31/3185 ,  G01R31/318525 ,  G11C7/1051 ,  G11C7/1066 ,  G11C29/40 ,  G11C29/48

摘要： Macro cells for a Double Data Rate (DDR) I/O interface are provided. The macro cells feature built-in self-test (BIST) functionality for testing the I/O interface at speed, without using external test or evaluation equipment. Each input or output macro cell is configured to generate test signals that are submitted to and processed by the I/O interface. The test signals are then dynamically compared to the signals produced by the interface in response to the test signals and a result is generated. The result may comprise an error signal if the test and response signals do not correspond. An I/O BIST controller may be employed to control the initiation and operation of the macro cells' self-testing.

摘要翻译： 提供了双数据速率（DDR）I / O接口的宏单元。 宏单元具有内置自检（BIST）功能，用于在不使用外部测试或评估设备的情况下快速测试I / O接口。 每个输入或输出宏单元被配置为生成提交给I / O接口并由其处理的测试信号。 然后将测试信号与响应于测试信号的接口产生的信号动态比较，并产生结果。 如果测试和响应信号不对应，则结果可以包括错误信号。 可以使用I / O BIST控制器来控制宏小区的自检的启动和操作。