公开(公告)号：US06587476B1

公开(公告)日：2003-07-01

申请号：US09320854

申请日：1999-05-26

申请人： Amit Lewin ,  Ilan Glaser ,  Yackov Sfadya ,  Yuri Poddobny

发明人： Amit Lewin ,  Ilan Glaser ,  Yackov Sfadya ,  Yuri Poddobny

IPC分类号： H04J316

CPC分类号： H04L12/289 ,  H04L12/2856 ,  H04L12/40136 ,  H04L12/413 ,  H04L12/4633

摘要： An apparatus for and method of encapsulating Ethernet frame data in HDLC frames for transmission over a VDSL transport facility. The HDLC frames are transmitted over a point to point VDSL link where they are subsequently extracted and forwarded as standard Ethernet frames. The VDSL facility transport system comprises one or more Ethernet to VDSL CPEs coupled to a DSLAM over a VDSL transport facility. The Ethernet to VDSL CPE functions to receive a 10BaseT Ethernet signal and encapsulate the Ethernet frame into a HDLC frame for transmission over the VDSL facility. In one embodiment, a single chip microcontroller on the CPE performs both Ethernet controller and HDLC controller functions. The DSLAM is adapted to receive HDLC frames from one or more CPEs, extract Ethernet frames therefrom and generate and output a standard Ethernet signal. Ethernet frames are encapsulated within HDLC frames and transmitted on the wire pair without regard to the state of the SOC signals. This overcomes the problems associated with synchronizing the transmission of the Ethernet data with the SOC signals.

摘要翻译： 一种用于将以太网帧数据封装在HDLC帧中以在VDSL传输设备上传输的装置和方法。 HDLC帧通过点到点VDSL链路发送，随后它们被提取并作为标准以太网帧转发。 VDSL设施传输系统包括通过VDSL传输设备耦合到DSLAM的一个或多个以太网到VDSL CPE。 以太网到VDSL CPE功能用于接收10BaseT以太网信号，并将以太网帧封装到HDLC帧中，以通过VDSL设备进行传输。 在一个实施例中，CPE上的单个芯片微控制器执行以太网控制器和HDLC控制器功能。 DSLAM适于从一个或多个CPE接收HDLC帧，从其中提取以太网帧，并生成并输出标准以太网信号。 以太网帧封装在HDLC帧内，并在线对上传输，而不考虑SOC信号的状态。 这克服了与以太网数据的传输与SOC信号同步的问题。

公开(公告)号：US06430198B1

公开(公告)日：2002-08-06

申请号：US08970545

申请日：1997-11-14

申请人： Yehuda Moyal ,  Ilan Glaser

发明人： Yehuda Moyal ,  Ilan Glaser

IPC分类号： H04J324

CPC分类号： H04L47/10 ,  H04L47/36

摘要： An apparatus for and a method of reducing the packet length count processing of data packets in a network device. The apparatus and method determine the length and end of a packet at the ingress point of the network computing device, e.g., a switch or router, using a single counting function. After the counting function verifies the length of the data packet, a signal indicating the length of a data packet is generated. This packet length indicator signal is then propagated throughout the system along with the data packet itself. The packet length indicator signal is then used at all decision points that involve the data packet. The packet length indicator signal itself is generated so as to indicate the beginning of the start of the data packet in addition to the end of the data packet, thus indicating the length of the packet. This obviates the need for the length of the packet to be counted over and over again in the course of processing the data packet within the switch or router.

摘要翻译： 一种用于减少网络设备中的数据分组的分组长度计数处理的装置和方法。 该装置和方法使用单个计数功能来确定网络计算设备（例如交换机或路由器）的入口点处的分组的长度和结束。 在计数功能验证数据包的长度之后，生成指示数据包的长度的信号。 然后，该数据包长度指示符信号与数据包本身一起在整个系统中传播。 然后在涉及数据分组的所有决策点使用分组长度指示符信号。 生成分组长度指示符信号本身，以便除了数据分组的结束之外还指示数据分组的开始开始，从而指示分组的长度。 这样就不需要在处理交换机或路由器内的数据包的过程中一次又一次地对数据包的长度进行计数。

公开(公告)号：US06807638B1

公开(公告)日：2004-10-19

申请号：US09751428

申请日：2000-12-29

申请人： Yehuda Moyal ,  Yehezkel Levi ,  Ilan Glaser ,  Simon Grinberg

发明人： Yehuda Moyal ,  Yehezkel Levi ,  Ilan Glaser ,  Simon Grinberg

IPC分类号： H04L700

CPC分类号： H04J3/0685 ,  H04J3/062

摘要： A novel and useful apparatus for and method of in-band clock compensation for use in synchronous communication systems. The clock compensation mechanism is implemented in each module and is operative to compensate for the differences between the clocks among the various modules in the system. The mechanism operates in band wherein special clock compensation symbols are periodically inserted into the data stream itself. Additional clock sync symbols are added to the data stream depending on the current level of the FIFO queue on the module or card. The insertion (or non-insertion) of additional symbols functions to compensate for the faster (or slower) clock of the module when compared to that of the reference.

摘要翻译： 一种用于同步通信系统中的带内时钟补偿的新颖有用的装置和方法。 时钟补偿机制在每个模块中实现，并且可用于补偿系统中各个模块之间的时钟之间的差异。 该机制在频带中操作，其中特殊时钟补偿符号被周期性地插入到数据流本身中。 根据模块或卡上的FIFO队列的当前级别，将额外的时钟同步符号添加到数据流。 附加符号的插入（或非插入）用于补偿与参考值相比更快（或更慢）的模块时钟。