公开(公告)号：US06807638B1

公开(公告)日：2004-10-19

申请号：US09751428

申请日：2000-12-29

申请人： Yehuda Moyal ,  Yehezkel Levi ,  Ilan Glaser ,  Simon Grinberg

发明人： Yehuda Moyal ,  Yehezkel Levi ,  Ilan Glaser ,  Simon Grinberg

IPC分类号： H04L700

CPC分类号： H04J3/0685 ,  H04J3/062

摘要： A novel and useful apparatus for and method of in-band clock compensation for use in synchronous communication systems. The clock compensation mechanism is implemented in each module and is operative to compensate for the differences between the clocks among the various modules in the system. The mechanism operates in band wherein special clock compensation symbols are periodically inserted into the data stream itself. Additional clock sync symbols are added to the data stream depending on the current level of the FIFO queue on the module or card. The insertion (or non-insertion) of additional symbols functions to compensate for the faster (or slower) clock of the module when compared to that of the reference.

摘要翻译： 一种用于同步通信系统中的带内时钟补偿的新颖有用的装置和方法。 时钟补偿机制在每个模块中实现，并且可用于补偿系统中各个模块之间的时钟之间的差异。 该机制在频带中操作，其中特殊时钟补偿符号被周期性地插入到数据流本身中。 根据模块或卡上的FIFO队列的当前级别，将额外的时钟同步符号添加到数据流。 附加符号的插入（或非插入）用于补偿与参考值相比更快（或更慢）的模块时钟。

公开(公告)号：US06834058B1

公开(公告)日：2004-12-21

申请号：US09751568

申请日：2000-12-29

申请人： Yehuda Moyal ,  Yehezkel Levi

发明人： Yehuda Moyal ,  Yehezkel Levi

IPC分类号： H04J306

CPC分类号： H04L49/9094 ,  H04L25/14 ,  H04L49/90

摘要： A novel and useful mechanism of synchronizing and aligning a plurality of data streams. The invention comprises a plurality of sync machines and an alignment circuit which in combination function to synchronize and align multiple variable length cell streams. Each sync machine is operative to control the output clocking of a corresponding FIFO queue. The data stream output of each FIFO queue is monitored by a sync machine and all the sync machines are coupled to the alignment circuit. In operation, the sync machines synchronize to the cells by searching for the error checks sequence (ECS) at the end of each cell. Upon synchronization being achieved for all the data streams, the alignment circuit causes each sync machine to freeze its respective FIFO until the ECS arrives on the data stream most delayed in time. Once the ECS is received on the slowest data stream, the alignment circuit releases the hold and consequently the FIFOs are released by the sync machines.

摘要翻译： 一种同步和对齐多个数据流的新颖有用的机制。 本发明包括多个同步机和对准电路，其组合起来能够同步和对准多个可变长度的单元流。 每个同步机可操作以控制对应的FIFO队列的输出时钟。 每个FIFO队列的数据流输出由同步机监视，并且所有同步机耦合到对准电路。 在操作中，同步机器通过搜索每个单元末端的错误检查序列（ECS）与单元同步。 在对所有数据流实现同步时，对准电路使每个同步机冻结其各自的FIFO，直到ECS到达数据流最为延迟的时间。 一旦在最慢的数据流上接收到ECS，对准电路释放保持，因此FIFO被同步器释放。

公开(公告)号：US07386711B1

公开(公告)日：2008-06-10

申请号：US10042846

申请日：2002-01-08

申请人： Moti Haimovsky ,  Yehezkel Levi ,  Doron Oz

发明人： Moti Haimovsky ,  Yehezkel Levi ,  Doron Oz

IPC分类号： G06F9/00

CPC分类号： G06F9/4416

摘要： The boot operations of one or more systems may be redirected. For example, a master boot processor may configure a slave boot processor to boot over a communication bus existing between the processors, which typically eliminates the need for boot software in slave systems. This can be accomplished such as by the master system updating a programmable interface of the slave system to identify an image from which to boot, such as from a remote boot image stored external to the slave system.

摘要翻译： 一个或多个系统的启动操作可以被重定向。 例如，主引导处理器可以将从引导处理器配置为通过存在于处理器之间的通信总线进行引导，这通常不需要从系统中的引导软件。 这可以通过主系统更新从系统的可编程接口来识别从其引导的图像，诸如从从系统外部存储的远程启动图像来实现。