公开(公告)号：US20200286889A1

公开(公告)日：2020-09-10

申请号：US16294431

申请日：2019-03-06

Applicant: Analog Devices, Inc.

Inventor： Javier A. Salcedo ,  Andrew Lewine

IPC: H01L27/092 ,  H01L29/87 ,  H01L27/02 ,  H01C7/12

Abstract: Electrical overstress protection for high speed applications, such as integrated multiple subsystem communications, is provided. In certain embodiments, a semiconductor die with distributed and configurable electrical overstress protection is provided. The semiconductor die includes signal pads, a core circuit electrically connected to the signal pads, and a configurable overstress protection array operable to protect the core circuit from electrical overstress at the signal pads. The configurable overstress protection array includes a plurality of segmented overstress protection devices of two or more different device types, and both a number of selected overstress protection devices and a device type of the selected overstress protection devices is programmable. The subsystems configurations are enabled in FinFET technology. Such configurable overstress protection arrays can be distributed across the die to protect not only core circuit sub-systems at the die pads, but also between internal sub-system communication interfaces operating in different power domains.

公开(公告)号：US11462535B2

公开(公告)日：2022-10-04

申请号：US17306563

申请日：2021-05-03

Applicant: Analog Devices, Inc.

Inventor： Javier A. Salcedo ,  Andrew Lewine

IPC: H01L27/092 ,  H01C7/12 ,  H01L27/02 ,  H01L29/87

Abstract: Electrical overstress protection for high speed applications is provided. In certain embodiments, a method of distributed and customizable electrical overstress protection for a semiconductor die is provided. The method includes configuring a heterogeneous overstress protection array that includes a customizable forward protection circuit electrically connected between a power high pad, a power low pad, and a signal pad and distributed across the semiconductor die, including selecting a number of segmented overstress protection devices from a plurality of available overstress protection devices of the customizable protection circuit. The method also includes choosing a device type of the selected segmented overstress protection devices from amongst two or more different device types providing complementary protection characteristics and protecting a core circuit from electrical overstress using the selected segmented overstress protection devices, the core circuit electrically connected to at least the signal pad, the power high pad, and the power low pad.

公开(公告)号：US20210257364A1

公开(公告)日：2021-08-19

申请号：US17306563

申请日：2021-05-03

Applicant: Analog Devices, Inc.

Inventor： Javier A. Salcedo ,  Andrew Lewine

IPC: H01L27/092 ,  H01L29/87 ,  H01L27/02 ,  H01C7/12

Abstract: Electrical overstress protection for high speed applications is provided. In certain embodiments, a method of distributed and customizable electrical overstress protection for a semiconductor die is provided. The method includes configuring a heterogeneous overstress protection array that includes a customizable forward protection circuit electrically connected between a power high pad, a power low pad, and a signal pad and distributed across the semiconductor die, including selecting a number of segmented overstress protection devices from a plurality of available overstress protection devices of the customizable protection circuit. The method also includes choosing a device type of the selected segmented overstress protection devices from amongst two or more different device types providing complementary protection characteristics and protecting a core circuit from electrical overstress using the selected segmented overstress protection devices, the core circuit electrically connected to at least the signal pad, the power high pad, and the power low pad.

公开(公告)号：US11004849B2

公开(公告)日：2021-05-11

申请号：US16294431

申请日：2019-03-06

Applicant: Analog Devices, Inc.

Inventor： Javier A. Salcedo ,  Andrew Lewine

IPC: H01L27/092 ,  H01C7/12 ,  H01L27/02 ,  H01L29/87

Abstract: Electrical overstress protection for high speed applications, such as integrated multiple subsystem communications, is provided. In certain embodiments, a semiconductor die with distributed and configurable electrical overstress protection is provided. The semiconductor die includes signal pads, a core circuit electrically connected to the signal pads, and a configurable overstress protection array operable to protect the core circuit from electrical overstress at the signal pads. The configurable overstress protection array includes a plurality of segmented overstress protection devices of two or more different device types, and both a number of selected overstress protection devices and a device type of the selected overstress protection devices is programmable. The subsystems configurations are enabled in FinFET technology. Such configurable overstress protection arrays can be distributed across the die to protect not only core circuit sub-systems at the die pads, but also between internal sub-system communication interfaces operating in different power domains.