公开(公告)号：US20190080231A1

公开(公告)日：2019-03-14

申请号：US16125621

申请日：2018-09-07

Applicant: Analog Devices, Inc.

Inventor： Eric G. NESTLER ,  Naveen VERMA ,  Hossein VALAVI

IPC: G06N3/063 ,  G06N3/06 ,  G11C11/54

Abstract: Systems and methods are provided for reducing power in in-memory computing, matrix-vector computations, and neural networks. An apparatus for in-memory computing using charge-domain circuit operation includes transistors configured as memory bit cells, transistors configured to perform in-memory computing using the memory bit cells, capacitors configured to store a result of in-memory computing from the memory bit cells, and switches, wherein, based on a setting of each of the switches, the charges on at least a portion of the plurality of capacitors are shorted together. Shorting together the plurality of capacitors yields a computation result.