公开(公告)号：US20170317683A1

公开(公告)日：2017-11-02

申请号：US15583183

申请日：2017-05-01

Applicant: Analog Devices, Inc.

Inventor： ABHISHEK BANDYOPADHYAY ,  Dan BOYKO ,  Eric G. NESTLER

IPC: H03M1/08 ,  H03M1/00

CPC classification number: H03M1/0854 ,  H03M1/002 ,  H03M1/468 ,  H03M3/426 ,  H03M3/458

Abstract: Systems and methods are disclosed for a noise-shaping successive approximation register (SAR) analog-to-digital-converter (ADC) using Sampled Analog Technology (SAT) filter techniques for filter construction. A SAR ADC includes an SAR for receiving an analog input signal and outputting a digital decision, a digital-to-analog converter and logic circuitry for converting the digital decision of the SAR to a present analog residue for a present conversion cycle, a filter for processing a previous analog residue from a previous conversion cycle, and for feeding a processed previous analog residue back to the SAR, a summer for summing the processed previous analog residue from the filter and the present analog residue, and generating a summer output, and a comparator for comparing the summer output and a first reference signal and generating a comparator output. The filter includes a capacitor array for filtering the previous analog residue to generate the processed previous analog residue.

公开(公告)号：US20170169327A1

公开(公告)日：2017-06-15

申请号：US15379114

申请日：2016-12-14

Applicant: Analog Devices, Inc.

Inventor： Eric G. NESTLER ,  Mitra M. OSQUI ,  Jeffrey G. BERNSTEIN

IPC: G06N3/04 ,  G06N3/063 ,  H03M1/80

CPC classification number: G06N3/04 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/0635 ,  H03M1/802

Abstract: Systems and methods of implementing a more efficient and less resource-intensive CNN are disclosed herein. In particular, applications of CNN in the analog domain using Sampled Analog Technology (SAT) methods are disclosed. Using a CNN design with SAT results in lower power usage and faster operation as compared to a CNN design with digital logic and memory. The lower power usage of a CNN design with SAT can allow for sensor devices that also detect features at very low power for isolated operation.

公开(公告)号：US20200249334A1

公开(公告)日：2020-08-06

申请号：US16840789

申请日：2020-04-06

Applicant: Analog Devices, Inc.

Inventor： Mikael MORTENSEN ,  Eric G. NESTLER ,  J. Brian HARRINGTON ,  Jeffrey G. BERNSTEIN

IPC: G01S7/52 ,  G01S15/89 ,  G10K11/34

Abstract: A system for ultrasound beamforming is provided, including a sampled analog beamformer, an array of ultrasound transducers, and a high voltage amplifier coupled to the sampled analog beamformer and the array of ultrasound transducers. The sampled analog beamformer includes a sampled analog filter for filtering an incoming analog signal and adding a fractional delay, and transmitting a filtered analog ultrasound signal. The array of ultrasound transducers further transmits the filtered analog ultrasound signal. The high voltage amplifier drives transducers in the array of ultrasound transducers.

公开(公告)号：US20190080231A1

公开(公告)日：2019-03-14

申请号：US16125621

申请日：2018-09-07

Applicant: Analog Devices, Inc.

Inventor： Eric G. NESTLER ,  Naveen VERMA ,  Hossein VALAVI

IPC: G06N3/063 ,  G06N3/06 ,  G11C11/54

Abstract: Systems and methods are provided for reducing power in in-memory computing, matrix-vector computations, and neural networks. An apparatus for in-memory computing using charge-domain circuit operation includes transistors configured as memory bit cells, transistors configured to perform in-memory computing using the memory bit cells, capacitors configured to store a result of in-memory computing from the memory bit cells, and switches, wherein, based on a setting of each of the switches, the charges on at least a portion of the plurality of capacitors are shorted together. Shorting together the plurality of capacitors yields a computation result.

公开(公告)号：US20180159473A1

公开(公告)日：2018-06-07

申请号：US15575312

申请日：2016-05-20

Applicant: Analog Devices, Inc.

Inventor： Eric G. NESTLER ,  Christopher Lynn MAGRUDER ,  John Brian HARRINGTON

IPC: H03D7/12 ,  H03H11/04 ,  H03H11/34

Abstract: Systems and methods for synchronous demodulation using passive sampled analog filtering are disclosed. A system for synchronous demodulation includes an input channel for accepting an input signal, a first passive sampled analog filter for filtering the input signal, a mixer for mixing the filtered input signal and outputting a mixed signal, a second passive sampled analog filter for filtering the mixed signal, and an output channel for outputting the filtered mixed signal.