公开(公告)号：US12072722B2

公开(公告)日：2024-08-27

申请号：US17901244

申请日：2022-09-01

Applicant: Analog Devices, Inc.

Inventor： Kevin R. Wrenner ,  Ruida Yun ,  Kenneth G. Richardson

IPC: G05F3/16 ,  G05F1/567 ,  G05F3/26

CPC classification number: G05F1/567 ,  G05F3/26 ,  G05F3/262

Abstract: Aspects of the present disclosure include a hybrid circuit, including a first current sink configured to sink a zero temperature coefficient (ZTC) current, a second current sink configured to sink a positive temperature coefficient (PTC) current, a first transistor configured to provide a first current, a second transistor configured to provide a second current, a third transistor configured to provide a third current mirroring the ZTC current, a fourth transistor configured to provide a sum current of the first current and the third current, and a current mirror configured provide a hybrid current mirroring the sum current.

公开(公告)号：US11789477B1

公开(公告)日：2023-10-17

申请号：US17901244

申请日：2022-09-01

Applicant: Analog Devices, Inc.

Inventor： Kevin R. Wrenner ,  Ruida Yun ,  Kenneth G. Richardson

IPC: G05F3/16 ,  G05F1/567 ,  G05F3/26

CPC classification number: G05F1/567 ,  G05F3/16 ,  G05F3/262

Abstract: Aspects of the present disclosure include a hybrid circuit, including a first current sink configured to sink a zero temperature coefficient (ZTC) current, a second current sink configured to sink a positive temperature coefficient (PTC) current, a first transistor configured to provide a first current, a second transistor configured to provide a second current, a third transistor configured to provide a third current mirroring the ZTC current, a fourth transistor configured to provide a sum current of the first current and the third current, and a current mirror configured provide a hybrid current mirroring the sum current.