公开(公告)号：US20040049293A1

公开(公告)日：2004-03-11

申请号：US10659533

申请日：2003-09-10

Applicant: Analog Devices, Inc.

Inventor： Rainer R. Hadwiger ,  Paul D. Krivacek ,  Joern Soerensen ,  Palle Birk

IPC: G05B019/18

CPC classification number: G06F13/385 ,  G06F13/36 ,  G06F15/7846 ,  H04W74/04

Abstract: A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masers each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.

Abstract translation: 多总线架构包括多个处理器，以及一个或多个共享外设，如存储器。 该架构包括多个总线主机，每个连接到自己的总线。 还有多个总线从站，每个都连接到自己的总线。 总线仲裁模块选择性地互连总线，使得当多个总线主机各访问不同的总线从机时，不发生阻塞，并且当多个总线主机每个访问相同的总线从机时，避免了带宽的不足。 该架构由总线仲裁方法支持，包括基于中断的方法的分层应用，分配的时隙旋转方法和循环方法，其避免在总线争用的长时间期间的带宽缺乏和锁定。