公开(公告)号：US20030095531A1

公开(公告)日：2003-05-22

申请号：US10300055

申请日：2002-11-20

Applicant: Analog Devices, Inc.

Inventor： Joern Soerensen ,  Palle Birk ,  Zoran Zvonar

IPC: H04B007/216

CPC classification number: H04B1/7115 ,  H04B2201/7071

Abstract: Methods and apparatus are provided for spread spectrum signal processing in a wireless communication system. The apparatus includes a control processor to generate commands for processing spread spectrum signal components and a reconfigurable coprocessor to process the spread spectrum signal components based on the commands and to provide reports to the control processor based on results of processing the signal components.

Abstract translation: 在无线通信系统中提供用于扩频信号处理的方法和装置。 该装置包括：控制处理器，用于产生用于处理扩展频谱信号分量的命令;以及可重构协处理器，用于基于该命令处理扩频信号分量，并根据处理信号分量的结果向控制处理器提供报告。

公开(公告)号：US20030071657A1

公开(公告)日：2003-04-17

申请号：US10231446

申请日：2002-08-29

Applicant: ANALOG DEVICES, INC.

Inventor： Joern Soerensen ,  Michael Allen ,  Palle Birk

IPC: H03K019/00

CPC classification number: G06F11/3636 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3869 ,  G06F9/4843 ,  G06F12/0842 ,  G06F12/0859 ,  G06F13/28 ,  G06F13/385 ,  G06F2213/3814 ,  H03L7/0802 ,  H03L7/095 ,  H03L7/183 ,  H04W88/06 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/24 ,  Y02D50/20 ,  Y02D70/1222 ,  Y02D70/124 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/164 ,  Y10S331/02

Abstract: A dynamic power controller is provided that identifies a clock frequency requirement of a processor and determines a voltage requirement to support the clock frequency requirement. The dynamic power controller transitions the processor to a power state defined by the clock frequency requirement and the voltage requirement. In particular, a voltage level indicated by the voltage requirement is supplied to the processor and the frequency distribution indicated by the frequency requirement is provided to the clocks signals of the processor.

Abstract translation: 提供了一种动态功率控制器，用于识别处理器的时钟频率要求，并确定支持时钟频率要求的电压要求。 动态功率控制器将处理器转换为由时钟频率要求和电压要求定义的功率状态。 特别地，由电压要求指示的电压电平被提供给处理器，并且由频率要求指示的频率分布被提供给处理器的时钟信号。

公开(公告)号：US20030058052A1

公开(公告)日：2003-03-27

申请号：US10230868

申请日：2002-08-29

Applicant: ANALOG DEVICES, INC.

Inventor： Palle Birk ,  Joern Soerensen

IPC: H03K021/00

CPC classification number: G06F11/3636 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3869 ,  G06F9/4843 ,  G06F12/0842 ,  G06F12/0859 ,  G06F13/28 ,  G06F13/385 ,  G06F2213/3814 ,  H03L7/0802 ,  H03L7/095 ,  H03L7/183 ,  H04W88/06 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/24 ,  Y02D50/20 ,  Y02D70/1222 ,  Y02D70/124 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/164 ,  Y10S331/02

Abstract: A PLL frequency multiplier is provided having a latency substantially equal to the wake-up time of the PLL. An operative clock signal is provided to a processor while the PLL is acquiring phase lock by insuring that the clock signal does not contain frequencies above a target frequency of a PLL and below a predetermined threshold frequency. In particular, a frequency divider and a frequency detector are provided to prevent the frequency of the clock signal from operating outside the range defined by the threshold and target frequencies.

Abstract translation: 提供PLL倍频器，其具有基本上等于PLL的唤醒时间的等待时间。 当PLL通过确保时钟信号不包含高于PLL的目标频率且低于预定阈值频率的频率来获取锁相时，将操作时钟信号提供给处理器。 特别地，提供了分频器和频率检测器以防止时钟信号的频率在阈值和目标频率所限定的范围之外运行。

公开(公告)号：US20040049293A1

公开(公告)日：2004-03-11

申请号：US10659533

申请日：2003-09-10

Applicant: Analog Devices, Inc.

Inventor： Rainer R. Hadwiger ,  Paul D. Krivacek ,  Joern Soerensen ,  Palle Birk

IPC: G05B019/18

CPC classification number: G06F13/385 ,  G06F13/36 ,  G06F15/7846 ,  H04W74/04

Abstract: A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masers each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.

Abstract translation: 多总线架构包括多个处理器，以及一个或多个共享外设，如存储器。 该架构包括多个总线主机，每个连接到自己的总线。 还有多个总线从站，每个都连接到自己的总线。 总线仲裁模块选择性地互连总线，使得当多个总线主机各访问不同的总线从机时，不发生阻塞，并且当多个总线主机每个访问相同的总线从机时，避免了带宽的不足。 该架构由总线仲裁方法支持，包括基于中断的方法的分层应用，分配的时隙旋转方法和循环方法，其避免在总线争用的长时间期间的带宽缺乏和锁定。