公开(公告)号：US20210194497A1

公开(公告)日：2021-06-24

申请号：US16074356

申请日：2017-02-01

申请人： Analog Devices Global Unlimited Company

发明人： David LAMB ,  Mayur ANVEKAR ,  Robert ADAMS

IPC分类号： H03M3/00 ,  H03H17/02 ,  H03H17/06

摘要： A variable output data rate converter circuit preferably meets performance requirements while keeping the circuit complexity low. In some embodiments, the converter circuit may include an oversampling sigma delta modulator circuit to quantize an analog input signal at an oversampled rate, and output an sigma delta modulated signal, a transposed polynomial decimator circuit to decimate the sigma delta modulated signal, and output a first decimated signal, and an integer decimator circuit to decimate the first decimated signal by an integer factor and output a second decimated signal having a desired output data rate. The transposed polynomial decimator circuit has a transposed polynomial filter circuit and a digital phase locked loop circuit, which tracks a ratio between a sampling rate of the first decimated signal and the oversampled rate, and outputs an intersample position parameter to the transposed polynomial filter circuit.