公开(公告)号：US20200059228A1

公开(公告)日：2020-02-20

申请号：US16238338

申请日：2019-01-02

申请人： Analog Devices Global Unlimited Company

发明人： Srivatsan Parthasarathy ,  Sirui Luo ,  Thomas Paul Kearney ,  Yuanzhong Zhou ,  Donal Bourke ,  Jean-Jacques Hajjar

IPC分类号： H03K17/081 ,  H03K17/0412

摘要： Fault tolerant switches are provided herein. In certain embodiments, a fault tolerant switch includes a switch, a gate driver, and a clamp. The switch includes a switch p-type field effect transistor (PFET) and a switch n-type field effect transistor (NFET) electrically connected in series and controlled by the gate driver. Additionally, the clamp is electrically connected in parallel with the switch, and includes a forward protection circuit including a first diode and a first clamp FET in series, and a reverse protection circuit including a second diode and a second clamp FET in series. The clamp further includes a first gate bias circuit configured to bias a gate of the first clamp FET and a second gate bias circuit configured to bias a gate of the second clamp FET.

公开(公告)号：US10581423B1

公开(公告)日：2020-03-03

申请号：US16238338

申请日：2019-01-02

申请人： Analog Devices Global Unlimited Company

发明人： Srivatsan Parthasarathy ,  Sirui Luo ,  Thomas Paul Kearney ,  Yuanzhong Zhou ,  Donal Bourke ,  Jean-Jacques Hajjar

IPC分类号： H01L27/02 ,  H02H9/00 ,  H03K17/081 ,  H03K17/0412

摘要： Fault tolerant switches are provided herein. In certain embodiments, a fault tolerant switch includes a switch, a gate driver, and a clamp. The switch includes a switch p-type field effect transistor (PFET) and a switch n-type field effect transistor (NFET) electrically connected in series and controlled by the gate driver. Additionally, the clamp is electrically connected in parallel with the switch, and includes a forward protection circuit including a first diode and a first clamp FET in series, and a reverse protection circuit including a second diode and a second clamp FET in series. The clamp further includes a first gate bias circuit configured to bias a gate of the first clamp FET and a second gate bias circuit configured to bias a gate of the second clamp FET.