公开(公告)号：US20150073739A1

公开(公告)日：2015-03-12

申请号：US14020404

申请日：2013-09-06

Applicant: Analog Devices Technology

Inventor： Muhammad Kalimuddin Khan ,  Kenneth J. Mulvaney ,  Michale Deeney ,  Niall Kevin Kearney

IPC: G01R23/02

CPC classification number: G01R23/02 ,  H03L7/095 ,  H03L7/193 ,  H03L7/1974 ,  H03L7/1976

Abstract: A monitoring circuit for monitoring the performance of a phase locked loop having a divider therein, the divider comprising at least a first counter, the monitoring circuit comprising at least one memory element for capturing a value of the first counter after a predetermined time from a system event in the operation of the phase locked loop, a variability calculator for comparing a value of the counter with a preceding value of the counter to calculate a variation, and a circuit responsive to the estimate of variation for outputting a status signal.

Abstract translation: 一种用于监视其中具有分频器的锁相环的性能的监视电路，所述分频器包括至少第一计数器，所述分频器包括至少一个存储器元件，用于在来自系统的预定时间之后捕获所述第一计数器的值 可变性计算器，用于将计数器的值与计数器的先前值进行比较以计算变化;以及电路，其响应于用于输出状态信号的变化估计。