公开(公告)号：US08255851B1

公开(公告)日：2012-08-28

申请号：US12490758

申请日：2009-06-24

申请人： Anan Baransy ,  Yaniv Uliel

发明人： Anan Baransy ,  Yaniv Uliel

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： Aspects of the disclosure provide a hold violation correction method that can save design time. The method can be integrated into early stages of electric circuit design instead of correcting hold violations during the final stages of circuit design prior to tape-out. The method can include constructing block-level input/output (IO) timing models for a plurality of circuit blocks that are interconnected, detecting one or more paths between the circuit blocks, adding one or more delay elements on the paths to cause that delays on the paths are within a predetermined delay target range.

摘要翻译： 本公开的方面提供了可以节省设计时间的保持违规校正方法。 该方法可以集成到电路设计的早期阶段，而不是在磁带输出之前在电路设计的最后阶段纠正保持违规。 该方法可以包括为互连的多个电路块构建块级输入/输出（IO）定时模型，检测电路块之间的一个或多个路径，在路径上添加一个或多个延迟元件以导致该延迟 路径在预定的延迟目标范围内。