公开(公告)号：US08255851B1

公开(公告)日：2012-08-28

申请号：US12490758

申请日：2009-06-24

申请人： Anan Baransy ,  Yaniv Uliel

发明人： Anan Baransy ,  Yaniv Uliel

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： Aspects of the disclosure provide a hold violation correction method that can save design time. The method can be integrated into early stages of electric circuit design instead of correcting hold violations during the final stages of circuit design prior to tape-out. The method can include constructing block-level input/output (IO) timing models for a plurality of circuit blocks that are interconnected, detecting one or more paths between the circuit blocks, adding one or more delay elements on the paths to cause that delays on the paths are within a predetermined delay target range.

摘要翻译： 本公开的方面提供了可以节省设计时间的保持违规校正方法。 该方法可以集成到电路设计的早期阶段，而不是在磁带输出之前在电路设计的最后阶段纠正保持违规。 该方法可以包括为互连的多个电路块构建块级输入/输出（IO）定时模型，检测电路块之间的一个或多个路径，在路径上添加一个或多个延迟元件以导致该延迟 路径在预定的延迟目标范围内。

公开(公告)号：US5488639A

公开(公告)日：1996-01-30

申请号：US171554

申请日：1993-12-21

申请人： Peter D. MacWilliams ,  Dror Avni ,  Avi Liebermensch ,  Anan Baransy ,  Robert L. Farrell

发明人： Peter D. MacWilliams ,  Dror Avni ,  Avi Liebermensch ,  Anan Baransy ,  Robert L. Farrell

IPC分类号： H04L7/02 ,  H04L7/033 ,  H04L7/00

CPC分类号： H04L7/02 ,  H04L7/0338 ,  H04L7/0337

摘要： A method and apparatus for synchronizing an asynchronous signal to a clock signal. The apparatus includes an enable generator, first, second and third sampling circuits, a selecting circuit, and can include a latching circuit. The enable generator is coupled to the first sampling circuit by a first enable line, to the second sampling circuit by a second enable line, and to the third sampling circuit by a third enable line. The first, second, and third sampling circuits are coupled to receive the asynchronous signal. The selecting circuit is coupled to receive the output signals of the first, second and third sampling circuits. For the first sampling circuit, the following steps are performed: sampling the asynchronous signal, generating an output signal for the sampling circuit, waiting a period of time, and selecting the sampling circuit's output signal. These steps are also performed for the second sampling circuit and the third sampling circuit.

摘要翻译： 一种用于将异步信号同步到时钟信号的方法和装置。 该装置包括使能发生器，第一，第二和第三采样电路，选择电路，并且可以包括锁存电路。 使能发生器通过第一使能线耦合到第一采样电路，通过第二使能线耦合到第二采样电路，并通过第三使能线耦合到第三采样电路。 第一，第二和第三采样电路被耦合以接收异步信号。 选择电路被耦合以接收第一，第二和第三采样电路的输出信号。 对于第一采样电路，执行以下步骤：对异步信号进行采样，产生采样电路的输出信号，等待一段时间，并选择采样电路的输出信号。 对于第二采样电路和第三采样电路也执行这些步骤。