BALANCED SENSE AMPLIFIER FOR SINGLE ENDED BITLINE MEMORY ARCHITECTURE
    1.
    发明申请
    BALANCED SENSE AMPLIFIER FOR SINGLE ENDED BITLINE MEMORY ARCHITECTURE 有权
    用于单端立体声存储器架构的平衡感测放大器

    公开(公告)号:US20100172199A1

    公开(公告)日:2010-07-08

    申请号:US12616696

    申请日:2009-11-11

    CPC classification number: G11C7/18 G11C7/02 G11C7/065

    Abstract: A balanced differential amplifier sense amplifier senses the voltage level in a selected single bit line memory cell. The output of the selected single bit-line memory cell is connected to one input of the balanced differential sense amplifier while the other input receives a reference voltage provided by a corresponding single bit-line memory cell from a complementary memory bank. A supporting voltage is added-to/subtracted-from the reference voltage by providing a “bump” or “dip” mechanism or by utilizing a charge-sharing structure, in order to compensate for the variation in the sensed bit-line voltage over the duration of the sensing interval as well as for the disparity in voltage level from cell to cell.

    Abstract translation: 平衡差分放大器读出放大器检测所选单位线存储单元中的电压电平。 所选择的单位线存储单元的输出连接到平衡差分读出放大器的一个输入端,而另一输入端从互补存储体接收由相应的单位线存储单元提供的参考电压。 通过提供“凸起”或“倾斜”机制或通过利用电荷共享结构,从参考电压加入/减去支持电压,以便补偿所检测到的位线电压的变化 感测间隔的持续时间以及从细胞到细胞的电压水平的差异。

    Balanced sense amplifier for single ended bitline memory architecture
    2.
    发明授权
    Balanced sense amplifier for single ended bitline memory architecture 有权
    用于单端位线存储器架构的平衡感测放大器

    公开(公告)号:US08144537B2

    公开(公告)日:2012-03-27

    申请号:US12616696

    申请日:2009-11-11

    CPC classification number: G11C7/18 G11C7/02 G11C7/065

    Abstract: A balanced differential amplifier sense amplifier senses the voltage level in a selected single bit line memory cell. The output of the selected single bit-line memory cell is connected to one input of the balanced differential sense amplifier while the other input receives a reference voltage provided by a corresponding single bit-line memory cell from a complementary memory bank. A supporting voltage is added-to/subtracted-from the reference voltage by providing a “bump” or “dip” mechanism or by utilizing a charge-sharing structure, in order to compensate for the variation in the sensed bit-line voltage over the duration of the sensing interval as well as for the disparity in voltage level from cell to cell.

    Abstract translation: 平衡差分放大器读出放大器检测所选单位线存储单元中的电压电平。 所选择的单位线存储单元的输出连接到平衡差分读出放大器的一个输入端,而另一输入端从互补存储体接收由相应的单位线存储单元提供的参考电压。 通过提供“凸起”或“倾斜”机制或通过利用电荷共享结构,从参考电压加入/减去支持电压,以便补偿所检测到的位线电压的变化 感测间隔的持续时间以及从细胞到细胞的电压水平的差异。

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