公开(公告)号：US20100165747A1

公开(公告)日：2010-07-01

申请号：US12721165

申请日：2010-03-10

申请人： Andrei Mihnea ,  William Kueber ,  Mark Helm

发明人： Andrei Mihnea ,  William Kueber ,  Mark Helm

IPC分类号： G11C16/04

CPC分类号： G11C16/3404 ,  G11C16/0483

摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.

摘要翻译： 本公开的实施例提供了用于治疗非易失性存储器单元的方法，装置，模块和系统。 一种方法包括以第一电压偏置耦合到一串存储器单元的第一选择栅极晶体管，以第二电压偏置耦合到串的第二选择栅极晶体管，将第一愈合电压施加到第一边缘字线，以便 提取在第一选择栅极晶体管和串的第一边缘存储单元堆之间累积的电荷，以及向第二边缘字线施加第二愈合电压，以便提取在第二选择栅极晶体管和第二边缘存储单元之间累积的电荷 堆栈的字符串。

公开(公告)号：US08542542B2

公开(公告)日：2013-09-24

申请号：US13567729

申请日：2012-08-06

申请人： Andrei Mihnea ,  William Kueber ,  Mark Helm

发明人： Andrei Mihnea ,  William Kueber ,  Mark Helm

IPC分类号： G11C11/34

CPC分类号： G11C16/3404 ,  G11C16/0483

摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.

摘要翻译： 本公开的实施例提供了用于治疗非易失性存储器单元的方法，装置，模块和系统。 一种方法包括以第一电压偏置耦合到一串存储器单元的第一选择栅极晶体管，以第二电压偏置耦合到串的第二选择栅极晶体管，将第一愈合电压施加到第一边缘字线，以便 提取在第一选择栅极晶体管和串的第一边缘存储单元堆之间累积的电荷，以及向第二边缘字线施加第二愈合电压，以便提取在第二选择栅极晶体管和第二边缘存储单元之间累积的电荷 堆栈的字符串。

公开(公告)号：US08238170B2

公开(公告)日：2012-08-07

申请号：US12721165

申请日：2010-03-10

申请人： Andrei Mihnea ,  William Kueber ,  Mark Helm

发明人： Andrei Mihnea ,  William Kueber ,  Mark Helm

IPC分类号： G11C11/34

CPC分类号： G11C16/3404 ,  G11C16/0483

摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.

摘要翻译： 本公开的实施例提供了用于治疗非易失性存储器单元的方法，装置，模块和系统。 一种方法包括以第一电压偏置耦合到一串存储器单元的第一选择栅极晶体管，以第二电压偏置耦合到串的第二选择栅极晶体管，将第一愈合电压施加到第一边缘字线，以便 提取在第一选择栅极晶体管和串的第一边缘存储单元堆之间累积的电荷，以及向第二边缘字线施加第二愈合电压，以便提取在第二选择栅极晶体管和第二边缘存储单元之间累积的电荷 堆栈的字符串。

公开(公告)号：US07701780B2

公开(公告)日：2010-04-20

申请号：US11809180

申请日：2007-05-31

申请人： Andrei Mihnea ,  William Kueber ,  Mark Helm

发明人： Andrei Mihnea ,  William Kueber ,  Mark Helm

IPC分类号： G11C16/04

CPC分类号： G11C16/3404 ,  G11C16/0483

摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.

摘要翻译： 本公开的实施例提供了用于治疗非易失性存储器单元的方法，装置，模块和系统。 一种方法包括以第一电压偏置耦合到一串存储器单元的第一选择栅极晶体管，以第二电压偏置耦合到串的第二选择栅极晶体管，将第一愈合电压施加到第一边缘字线，以便 提取在第一选择栅极晶体管和串的第一边缘存储单元堆之间累积的电荷，以及向第二边缘字线施加第二愈合电压，以便提取在第二选择栅极晶体管和第二边缘存储单元之间累积的电荷 堆栈的字符串。

公开(公告)号：US20080298123A1

公开(公告)日：2008-12-04

申请号：US11809180

申请日：2007-05-31

申请人： Andrei Mihnea ,  William Kueber ,  Mark Helm

发明人： Andrei Mihnea ,  William Kueber ,  Mark Helm

IPC分类号： G11C11/34

CPC分类号： G11C16/3404 ,  G11C16/0483

摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.

摘要翻译： 本公开的实施例提供了用于治疗非易失性存储器单元的方法，装置，模块和系统。 一种方法包括以第一电压偏置耦合到一串存储器单元的第一选择栅极晶体管，以第二电压偏置耦合到串的第二选择栅极晶体管，将第一愈合电压施加到第一边缘字线，以便 提取在第一选择栅极晶体管和串的第一边缘存储单元堆之间累积的电荷，以及向第二边缘字线施加第二愈合电压，以便提取在第二选择栅极晶体管和第二边缘存储单元之间累积的电荷 堆栈的字符串。

公开(公告)号：US20120300551A1

公开(公告)日：2012-11-29

申请号：US13567729

申请日：2012-08-06

申请人： Andrei Mihnea ,  William Kueber ,  Mark Helm

发明人： Andrei Mihnea ,  William Kueber ,  Mark Helm

IPC分类号： G11C16/04

CPC分类号： G11C16/3404 ,  G11C16/0483

摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.

摘要翻译： 本公开的实施例提供了用于治疗非易失性存储器单元的方法，装置，模块和系统。 一种方法包括以第一电压偏置耦合到一串存储器单元的第一选择栅极晶体管，以第二电压偏置耦合到串的第二选择栅极晶体管，将第一愈合电压施加到第一边缘字线，以便 提取在第一选择栅极晶体管和串的第一边缘存储单元堆之间累积的电荷，并且向第二边缘字线施加第二愈合电压，以便提取在第二选择栅极晶体管和第二边缘存储单元之间累积的电荷 堆栈的字符串。

公开(公告)号：US08139421B2

公开(公告)日：2012-03-20

申请号：US12906497

申请日：2010-10-18

申请人： Andrei Mihnea ,  William Kueber

发明人： Andrei Mihnea ,  William Kueber

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/16 ,  G11C16/344

摘要： Methods for erasing a memory device and memory systems are provided, such as those including a non-volatile memory device is erased by using an intermediate erase step prior to a normal erase step. The intermediate erase step is comprised of an erase pulse voltage, applied to the semiconductor well of the selected memory block of memory cells, while edge rows of memory cells are biased at a low positive voltage (e.g., 0.2-2V). An erase verify operation is then performed. If the selected memory block is not erased, a normal memory erase step is then performed in which the same erase pulse voltage is used but all of the rows are biased at ground potential as in a normal erase step. If the memory block is still fails the erase verify operation, the erase pulse voltage is increased and the process repeated.

摘要翻译： 提供了用于擦除存储器件和存储器系统的方法，诸如包括非易失性存储器件的那些方法在通常擦除步骤之前通过使用中间擦除步骤被擦除。 中间擦除步骤包括施加到存储器单元的所选存储块的半导体阱的擦除脉冲电压，而边沿行的存储器单元被偏置在低正电压（例如，0.2-2V）。 然后执行擦除验证操作。 如果所选择的存储器块未被擦除，则执行正常的存储器擦除步骤，其中使用相同的擦除脉冲电压，但是所有行都像正常擦除步骤那样被偏置在地电位。 如果存储器块仍然失效，擦除验证操作，擦除脉冲电压就会增加，重复处理。

公开(公告)号：US20110032768A1

公开(公告)日：2011-02-10

申请号：US12906497

申请日：2010-10-18

申请人： Andrei Mihnea ,  William Kueber

发明人： Andrei Mihnea ,  William Kueber

IPC分类号： G11C16/14 ,  G11C16/34

CPC分类号： G11C16/0483 ,  G11C16/16 ,  G11C16/344

摘要： Methods for erasing a memory device and memory systems are provided, such as those including a non-volatile memory device is erased by using an intermediate erase step prior to a normal erase step. The intermediate erase step is comprised of an erase pulse voltage, applied to the semiconductor well of the selected memory block of memory cells, while edge rows of memory cells are biased at a low positive voltage (e.g., 0.2-2V). An erase verify operation is then performed. If the selected memory block is not erased, a normal memory erase step is then performed in which the same erase pulse voltage is used but all of the rows are biased at ground potential as in a normal erase step. If the memory block is still fails the erase verify operation, the erase pulse voltage is increased and the process repeated.

摘要翻译： 提供了用于擦除存储器件和存储器系统的方法，诸如包括非易失性存储器件的那些方法在通常擦除步骤之前通过使用中间擦除步骤被擦除。 中间擦除步骤包括施加到存储器单元的所选存储块的半导体阱的擦除脉冲电压，而边沿行的存储器单元被偏置在低正电压（例如，0.2-2V）。 然后执行擦除验证操作。 如果所选择的存储器块未被擦除，则执行正常的存储器擦除步骤，其中使用相同的擦除脉冲电压，但是所有行都像正常擦除步骤那样被偏置在地电位。 如果存储器块仍然失效，擦除验证操作，擦除脉冲电压就会增加，重复处理。

公开(公告)号：US07817478B2

公开(公告)日：2010-10-19

申请号：US12058839

申请日：2008-03-31

申请人： Andrei Mihnea ,  William Kueber

发明人： Andrei Mihnea ,  William Kueber

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/16 ,  G11C16/344

摘要： Methods for erasing a memory device and memory systems are provided, such as those including a non-volatile memory device is erased by using an intermediate erase step prior to a normal erase step. The intermediate erase step is comprised of an erase pulse voltage, applied to the semiconductor well of the selected memory block of memory cells, while edge rows of memory cells are biased at a low positive voltage (e.g., 0.8-2V). An erase verify operation is then performed. If the selected memory block is not erased, a normal memory erase step is then performed in which the same erase pulse voltage is used but all of the rows are biased at ground potential as in a normal erase step. If the memory block is still fails the erase verify operation, the erase pulse voltage is increased and the process repeated.

摘要翻译： 提供了用于擦除存储器件和存储器系统的方法，诸如包括非易失性存储器件的那些方法在通常擦除步骤之前通过使用中间擦除步骤被擦除。 中间擦除步骤包括施加到存储器单元的选定存储块的半导体阱的擦除脉冲电压，而边沿行的存储器单元被偏置在低正电压（例如0.8-2V）。 然后执行擦除验证操作。 如果所选择的存储器块未被擦除，则执行正常的存储器擦除步骤，其中使用相同的擦除脉冲电压，但是所有行都像正常擦除步骤那样被偏置在地电位。 如果存储器块仍然失效，擦除验证操作，擦除脉冲电压就会增加，重复处理。

公开(公告)号：US20090244979A1

公开(公告)日：2009-10-01

申请号：US12058839

申请日：2008-03-31

申请人： Andrei Mihnea ,  William Kueber

发明人： Andrei Mihnea ,  William Kueber

IPC分类号： G11C16/14 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/16 ,  G11C16/344

摘要： Methods for erasing a memory device and memory systems are provided, such as those including a non-volatile memory device is erased by using an intermediate erase step prior to a normal erase step. The intermediate erase step is comprised of an erase pulse voltage, applied to the semiconductor well of the selected memory block of memory cells, while edge rows of memory cells are biased at a low positive voltage (e.g., 0.8-2V). An erase verify operation is then performed. If the selected memory block is not erased, a normal memory erase step is then performed in which the same erase pulse voltage is used but all of the rows are biased at ground potential as in a normal erase step. If the memory block is still fails the erase verify operation, the erase pulse voltage is increased and the process repeated.

摘要翻译： 提供了用于擦除存储器件和存储器系统的方法，诸如包括非易失性存储器件的那些方法在通常擦除步骤之前通过使用中间擦除步骤被擦除。 中间擦除步骤包括施加到存储器单元的选定存储块的半导体阱的擦除脉冲电压，而边沿行的存储器单元被偏置在低正电压（例如0.8-2V）。 然后执行擦除验证操作。 如果所选择的存储器块未被擦除，则执行正常的存储器擦除步骤，其中使用相同的擦除脉冲电压，但是所有行都像正常擦除步骤那样被偏置在地电位。 如果存储器块仍然失效，擦除验证操作，擦除脉冲电压就会增加，重复处理。