-
1.发明授权Multi-phase clock distribution method and system for complex integrated-circuit devices 失效复杂集成电路设备的多相时钟分配方法和系统
公开(公告)号：US5966522A
公开(公告)日：1999-10-12
申请号：US828915
申请日：1997-03-28
CPC分类号： G06F1/10 , G06F17/5077 , H01L27/0207
摘要： A system and method are provided for distributing clock signals within integrated circuitry. The system includes a number of cells for the integrated circuitry such that the cells include substantially horizontal regions within which are disposed substantially horizontal lines representative of a first clock. The cells also include substantially vertical regions within which are disposed vertical lines representative of a second clock. The cells are disposed in substantially horizontal layers. The vertical regions, including the vertical lines representative of a second clock are substantially vertically aligned. The cells include circuitry disposed within each cell such that a first portion of such circuitry includes signal wiring, and a second portion of such circuitry includes clock wiring, and such that the disposition of said circuitry minimizes a cumulative length of signal wiring and clock wiring.
摘要翻译： 提供了用于在集成电路内分配时钟信号的系统和方法。 该系统包括用于集成电路的多个单元，使得单元包括基本上水平的区域，其中基本上水平地布置有代表第一时钟的线。 单元还包括基本上垂直的区域，其中设置了表示第二时钟的垂直线。 电池被设置在大致水平的层中。 包括表示第二时钟的垂直线的垂直区域基本上垂直对齐。 单元包括设置在每个单元内的电路，使得这种电路的第一部分包括信号布线，并且这种电路的第二部分包括时钟布线，并且使得所述电路的布置使信号布线和时钟布线的累积长度最小化。
-
公开(公告)号：US6018621A
公开(公告)日：2000-01-25
申请号：US761891
申请日：1996-12-09
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： At least one certain type of logic gates, such as NOT gates, in a network of logic gates are moved to the network inputs and outputs, by converting the logic gates in the network to certain types of gates, such as AND, OR and NOT gates. A region in the network is identified for selecting, within the region, between propagating the one certain type of gates to a) the network inputs, and b) the network outputs. The region is identified in response to "reconvergent fanout nodes". A reconvergent fanout node defines a loop having two branches which diverge at the node and reconverge thereafter.
摘要翻译： 通过将网络中的逻辑门转换为某些类型的门，例如AND，OR和NOT，逻辑门网络中的至少一种某种类型的逻辑门（例如NOT门）被移动到网络输入和输出 大门 网络中的区域被识别用于在区域内选择传播一种特定类型的门到a）网络输入，以及b）网络输出。 响应于“重新启动扇出节点”识别该区域。 再聚合扇出节点定义了一个具有两个分支的循环，该分支在节点处发散，此后重新收敛。
-
公开(公告)号：US6035110A
公开(公告)日：2000-03-07
申请号：US761890
申请日：1996-12-09
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A certain type of gates, such as NOT gates, in a logic network are moved to the network boundary (i.e., inputs or outputs), at least in part, by selecting nodes in the network as candidate nodes for choosing among to determine output phase assignments. Such a candidate node is selected in response to non-reconvergence of branches fanning out from the node.
摘要翻译： 至少部分地，通过选择网络中的节点作为用于选择的候选节点来确定输出相位，逻辑网络中的某些类型的门（例如NOT门）被移动到网络边界（即，输入或输出） 作业。 响应于从节点扇出的分支的非重新收敛来选择这样的候选节点。
-
公开(公告)号：US5896046A
公开(公告)日：1999-04-20
申请号：US790259
申请日：1997-01-27
申请人： Andrew Augustus Bjorksten , Michael Kevin Ciraula , Christopher McCall Durham , Donald George Mikan, Jr.
发明人： Andrew Augustus Bjorksten , Michael Kevin Ciraula , Christopher McCall Durham , Donald George Mikan, Jr.
IPC分类号： H03K3/356 , H03K19/096
CPC分类号： H03K19/0963 , H03K3/356121
摘要： A method and implementing structure for a domino block circuit 200 includes a minimal component latching circuit 203 which is merged with an exemplary MUX functional block 201, to provide both inverting and latching functions with minimal propagation delay in the domino data path. Implementations with scanning circuitry and including a holding feature are also illustrated.
摘要翻译： 多米诺骨牌电路200的方法和实现结构包括与示例性MUX功能块201合并的最小分量锁存电路203，以提供多米诺骨牌数据路径中具有最小传播延迟的反转和锁存功能。 还示出了具有扫描电路并包括保持特征的实现。
-
公开(公告)号：US5903467A
公开(公告)日：1999-05-11
申请号：US763980
申请日：1996-12-10
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： In designing a logic network a plurality of nodes are identified which define incompatible output phase assignments. Certain of the incompatible nodes are selected for assigning the output phases, so that NOT gates in the fan-out cone of such a selected node are moved to the network outputs. In a further aspect, the selecting is in response to the number of logic gates in the fan-in cones of the incompatible nodes.
摘要翻译： 在设计逻辑网络时，识别出定义不兼容的输出相位分配的多个节点。 选择某些不兼容的节点用于分配输出相位，使得这样选择的节点的扇出锥的NOT门被移动到网络输出。 在另一方面，该选择是响应于不兼容节点的扇入锥中的逻辑门数。
-
6.发明授权Method and system for interchanging operands during complex instruction execution in a data processing system 失效在数据处理系统中复杂指令执行期间交换操作数的方法和系统
公开(公告)号：US5771366A
公开(公告)日：1998-06-23
申请号：US489181
申请日：1995-06-09
CPC分类号： G06F9/3001 , G06F9/3017 , G06F9/3836 , G06F9/384
摘要： A method and system for interchanging operands and loading such operands into a plurality of operand registers in an execution unit with the data processing system during execution of a complex instruction. A plurality of operands are stored within a register file, including a first operand and a second operand. An instruction is loaded into the first stage of the execution pipe within the execution unit, wherein the instruction has a plurality of fields. Such fields include a first and second field, containing a first and second operand pointer, respectively, for designating a value stored in the register file for loading into first and second operand registers, respectively. Next, the first and second operand pointers are interchanged between the first and second fields. Finally, the first operand register is loaded with the value in the register file designated by the second operand pointer stored in the first field, and the second operand register is loaded with the value in the register file designated by the first operand pointer in the second field, wherein the values in the register file designated by operand pointers in the fields of the instruction are loaded into different operand registers than originally specified by the instruction, thereby facilitating execution of a complex instruction in the execution unit.
摘要翻译： 一种方法和系统，用于在执行复杂指令期间将所述操作数互换并将所述操作数加载到与所述数据处理系统的执行单元中的多个操作数寄存器中。 多个操作数存储在寄存器文件中，包括第一操作数和第二操作数。 指令被加载到执行单元内的执行管道的第一级，其中指令具有多个场。 这些字段包括分别包含第一和第二操作数指针的第一和第二字段，用于分别指定存储在寄存器文件中的值以加载到第一和第二操作数寄存器中。 接下来，第一和第二操作数指针在第一和第二字段之间互换。 最后，第一个操作数寄存器加载存储在第一个字段中的第二个操作数指针所指定的寄存器文件中的值，第二个操作数寄存器被加载在第二个操作数指针指定的寄存器文件中的值 字段，其中由指令字段中的操作数指针指定的寄存器文件中的值被加载到与指令最初指定的不同的操作数寄存器中，从而便于在执行单元中执行复杂指令。
-
-
-
-
-
搜索结果
6 条记录 (耗时 0.024 秒)
