公开(公告)号：US5703872A

公开(公告)日：1997-12-30

申请号：US598293

申请日：1996-02-08

申请人： Andrew Keith Boggs ,  Quy N. Hoang ,  Joe Jacobs ,  John Mark Mullen ,  Challis Purrington ,  Laura A. Weaver

发明人： Andrew Keith Boggs ,  Quy N. Hoang ,  Joe Jacobs ,  John Mark Mullen ,  Challis Purrington ,  Laura A. Weaver

IPC分类号： H04L29/08 ,  H04L12/433 ,  H04L29/00 ,  H04L29/06 ,  H04L12/42

CPC分类号： H04L29/00 ,  H04L12/433 ,  H04L69/18

摘要： An intelligent multistation access unit is provided having a transmission speed detection circuit for determining the data transmission speed of an attached device attempting to gain access to a node of a multiple transmission rate digital data communications network. The intelligent multistation access unit is comprised of a speed detect circuit, which indicates the data transmission speed of the attached device, a switching circuit which directs the attached device to the speed detect circuit until switched to allow the attached device access to the network node, and a processor that controls the switching circuit and which permits the attached device access to the node depending on the data transmission speed indication.

摘要翻译： 提供一种具有传输速度检测电路的智能多路访问单元，该传输速度检测电路用于确定试图访问多传输速率数字数据通信网络的节点的连接设备的数据传输速度。 智能多路访问单元包括速度检测电路，其指示所连接设备的数据传输速度;切换电路，其将连接的设备引导到速度检测电路，直到切换为允许所连接的设备接入网络节点; 以及处理器，其控制切换电路，并且允许所附接的设备根据数据传输速度指示访问节点。

公开(公告)号：US06192035B1

公开(公告)日：2001-02-20

申请号：US08900204

申请日：1997-07-24

申请人： Andrew Keith Boggs ,  Quy N. Hoang ,  Joe Jacobs ,  John Mark Mullen ,  Challis Purrington ,  Laura A. Weaver

发明人： Andrew Keith Boggs ,  Quy N. Hoang ,  Joe Jacobs ,  John Mark Mullen ,  Challis Purrington ,  Laura A. Weaver

IPC分类号： H04L1242

CPC分类号： H04L29/06 ,  H04L12/433 ,  H04L69/18 ,  H04L69/323

摘要： An intelligent multistation access unit is provided having a transmission speed detection circuit for determining the data transmission speed of an attached device attempting to gain access to a node of a multiple transmission rate digital data communications network. The intelligent multistation access unit is comprised of a speed detect circuit, which indicates the data transmission speed of the attached device, a switching circuit which directs the attached device to the speed detect circuit until switched to allow the attached device access to the network node, and a processor that controls the switching circuit and which permits the attached device access to the node depending on the data transmission speed indication.

摘要翻译： 提供一种具有传输速度检测电路的智能多路访问单元，该传输速度检测电路用于确定试图访问多传输速率数字数据通信网络的节点的连接设备的数据传输速度。 智能多路访问单元包括速度检测电路，其指示所连接设备的数据传输速度;切换电路，其将连接的设备引导到速度检测电路，直到切换为允许所连接的设备接入网络节点; 以及处理器，其控制切换电路，并且允许所附接的设备根据数据传输速度指示访问节点。

公开(公告)号：US5530696A

公开(公告)日：1996-06-25

申请号：US263704

申请日：1994-06-22

申请人： Andrew K. Boggs ,  Quy N. Hoang ,  Joe Jacobs ,  John M. Mullen ,  Challis Purrington ,  Laura A. Weaver

发明人： Andrew K. Boggs ,  Quy N. Hoang ,  Joe Jacobs ,  John M. Mullen ,  Challis Purrington ,  Laura A. Weaver

IPC分类号： H04L29/08 ,  H04L12/433 ,  H04L29/00 ,  H04L29/06 ,  H04L12/42

CPC分类号： H04L29/00 ,  H04L12/433 ,  H04L69/18

摘要： An intelligent multistation access unit is provided having a transmission speed detection circuit for determining the data transmission speed of an attached device attempting to gain access to a node of a multiple transmission rate digital data communications network. The intelligent multistation access unit is comprised of a speed detect circuit, which indicates the data transmission speed of the attached device, a switching circuit which directs the attached device to the speed detect circuit until switched to allow the attached device access to the network node, and a processor that controls the switching circuit and which permits the attached device access to the node depending on the data transmission speed indication.

摘要翻译： 提供一种具有传输速度检测电路的智能多路访问单元，该传输速度检测电路用于确定试图访问多传输速率数字数据通信网络的节点的连接设备的数据传输速度。 智能多路访问单元包括速度检测电路，其指示所连接设备的数据传输速度;切换电路，其将连接的设备引导到速度检测电路，直到切换为允许所连接的设备接入网络节点; 以及处理器，其控制切换电路，并且允许所附接的设备根据数据传输速度指示访问节点。

公开(公告)号：US20080147996A1

公开(公告)日：2008-06-19

申请号：US12037309

申请日：2008-02-26

申请人： Steven K. Jenkins ,  Laura A. Weaver

发明人： Steven K. Jenkins ,  Laura A. Weaver

IPC分类号： G06F12/00

CPC分类号： G06F13/1652

摘要： Efficient transfer of data to and from random access memory is described. Multiple request sources and a memory system comprise memory modules having memory banks, each bank containing rows of data. The retrieval comprises transferring all data pursuant to a given request by one source before any data is transferred pursuant to a subsequent request from said second source. This retrieval is achieved using a memory arbiter that implements an algorithm for atomic read/write. Each bank is assigned a FIFO buffer by the arbiter to store access requests. The access requests are arbitrated, and an encoded value of a winner of arbitration is loaded into the relevant FIFO buffer(s) before choosing the next winner. When an encoded value reaches the head of the buffer, all associated data is accessed in the given bank before accessing data for another request source.

摘要翻译： 描述了向/从随机存取存储器的有效数据传输。 多个请求源和存储器系统包括具有存储体的存储器模块，每个存储体包含数据行。 所述检索包括在根据来自所述第二源的后续请求传送任何数据之前，根据一个源的给定请求传送所有数据。 该检索使用实现原子读/写算法的存储器仲裁器来实现。 每个存储体由仲裁器分配一个FIFO缓冲区以存储访问请求。 对访问请求进行仲裁，并且在选择下一个获胜者之前将仲裁胜者的编码值加载到相关的FIFO缓冲区中。 当编码值到达缓冲区的头部时，在访问另一个请求源的数据之前，在给定的存储体中访问所有关联的数据。

公开(公告)号：US07660951B2

公开(公告)日：2010-02-09

申请号：US12037309

申请日：2008-02-26

申请人： Steven K. Jenkins ,  Laura A. Weaver

发明人： Steven K. Jenkins ,  Laura A. Weaver

IPC分类号： G06F13/00

CPC分类号： G06F13/1652

摘要： Efficient transfer of data to and from random access memory is described. Multiple request sources and a memory system comprise memory modules having memory banks, each bank containing rows of data. The retrieval comprises transferring all data pursuant to a given request by one source before any data is transferred pursuant to a subsequent request from said second source. This retrieval is achieved using a memory arbiter that implements an algorithm for atomic read/write. Each bank is assigned a FIFO buffer by the arbiter to store access requests. The access requests are arbitrated, and an encoded value of a winner of arbitration is loaded into the relevant FIFO buffer(s) before choosing the next winner. When an encoded value reaches the head of the buffer, all associated data is accessed in the given bank before accessing data for another request source.

摘要翻译： 描述了向/从随机存取存储器的有效数据传送。 多个请求源和存储器系统包括具有存储体的存储器模块，每个存储体包含数据行。 所述检索包括在根据来自所述第二源的后续请求传送任何数据之前，根据一个源的给定请求传送所有数据。 该检索使用实现原子读/写算法的存储器仲裁器来实现。 每个存储体由仲裁器分配一个FIFO缓冲区以存储访问请求。 对访问请求进行仲裁，并且在选择下一个获胜者之前将仲裁胜者的编码值加载到相关的FIFO缓冲区中。 当编码值到达缓冲区的头部时，在访问另一个请求源的数据之前，在给定的存储体中访问所有关联的数据。

公开(公告)号：US07360035B2

公开(公告)日：2008-04-15

申请号：US10931705

申请日：2004-09-01

申请人： Steven K. Jenkins ,  Laura A. Weaver

发明人： Steven K. Jenkins ,  Laura A. Weaver

IPC分类号： G06F13/00

CPC分类号： G06F13/1652

摘要： Efficient transfer of data to and from random access memory is described. Multiple request sources and a memory system comprise memory modules having memory banks, each bank containing rows of data. The retrieval comprises transferring all data pursuant to a given request by one source before any data is transferred pursuant to a subsequent request from said second source. This retrieval is achieved using a memory arbiter that implements an algorithm for atomic read/write. Each bank is assigned a FIFO buffer by the arbiter to store access requests. The access requests are arbitrated, and an encoded value of a winner of arbitration is loaded into the relevant FIFO buffer(s) before choosing the next winner. When an encoded value reaches the head of the buffer, all associated data is accessed in the given bank before accessing data for another request source.

摘要翻译： 描述了向/从随机存取存储器的有效数据传输。 多个请求源和存储器系统包括具有存储体的存储器模块，每个存储体包含数据行。 所述检索包括在根据来自所述第二源的后续请求传送任何数据之前，根据一个源的给定请求传送所有数据。 该检索使用实现原子读/写算法的存储器仲裁器来实现。 每个存储体由仲裁器分配一个FIFO缓冲区以存储访问请求。 对访问请求进行仲裁，并且在选择下一个获胜者之前将仲裁胜者的编码值加载到相关的FIFO缓冲区中。 当编码值到达缓冲区的头部时，在访问另一个请求源的数据之前，在给定的存储体中访问所有关联的数据。