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公开(公告)号：US08032713B2
公开(公告)日：2011-10-04
申请号：US12115146
申请日：2008-05-05
IPC分类号： G06F12/00
CPC分类号： G06F12/0862
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a storage device, circuitry for providing a speculative access threshold corresponding to a selected percentage of the total number of accesses to the storage device that can be speculatively issued, and circuitry for intermixing demand accesses and speculative accesses in accordance with the speculative access threshold.
摘要翻译： 提供了体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构。 该设计结构通常包括计算机系统，其包括CPU，存储设备，用于提供与可推测发布的对存储设备的访问总数的所选百分比相对应的推测访问阈值的电路，以及用于混合需求的电路 根据投机访问阈值访问和推测访问。
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2.发明授权Structure for data bus bandwidth scheduling in an FBDIMM memory system operating in variable latency mode 有权在可变延迟模式下工作的FBDIMM存储器系统中数据总线带宽调度的结构公开(公告)号：US08028257B2
公开(公告)日：2011-09-27
申请号：US12110765
申请日：2008-04-28
CPC分类号： G06F13/1689
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for scheduling the servicing of data requests, using the variable latency mode, in an FBDIMM memory sub-system is provided. A scheduling algorithm pre-computes return time data for data connected to DRAM buffer chips and stores the return time data in a table. The return time data is expressed as data return time binary vectors with one bit equal to “1” in each vector. For each received data request, the memory controller retrieves the appropriate return time vector. Additionally, the scheduling algorithm utilizes an updated history vector to determine whether the received request presents a conflict to the executing requests. By computing and utilizing a score for each request, the scheduling algorithm re-orders and schedules the execution of selected requests to preserve as much data bus bandwidth as possible, while avoiding conflict.
摘要翻译： 提供了一种体现在机器可读存储介质中的设计结构，用于在FBDIMM存储器子系统中使用可变延迟模式来设计，制造和/或测试用于调度数据请求的服务的设计。 调度算法预先计算连接到DRAM缓冲器芯片的数据的返回时间数据，并将返回时间数据存储在表中。 返回时间数据表示为在每个向量中一位等于“1”的数据返回时间二进制向量。 对于每个接收到的数据请求，存储器控制器检索适当的返回时间向量。 此外，调度算法利用更新的历史向量来确定接收到的请求是否对执行请求产生冲突。 通过计算和利用每个请求的分数，调度算法重新排序和调度所选择的请求的执行，以尽可能地保留尽可能多的数据总线带宽，同时避免冲突。
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3.发明申请DATA BUS BANDWIDTH SCHEDULING IN AN FBDIMM MEMORY SYSTEM OPERATING IN VARIABLE LATENCY MODE 失效在可变延迟模式下操作的FBDIMM存储器系统中的数据总线带宽调度公开(公告)号：US20080215832A1
公开(公告)日：2008-09-04
申请号：US11680695
申请日：2007-03-01
IPC分类号： G06F12/00
CPC分类号： G06F13/4243
摘要： A method and system for scheduling the servicing of data requests, using the variable latency mode, in an FBDIMM memory sub-system. A scheduling algorithm pre-computes return time data for data connected to all DRAM buffer chips and stores the return time data in a table. The return time data is expressed as a set of data return time binary vectors with one bit equal to “1” in each vector. For each received data request, the memory controller retrieves the appropriate return time vector. Additionally, the scheduling algorithm utilizes an updated history vector representing a compilation of data return time vectors of all executing requests to determine whether the received request presents a conflict to the executing requests. By computing and utilizing a score for each request, the scheduling algorithm re-orders and schedules the execution of selected requests to preserve as much data bus bandwidth as possible, while avoiding conflict.
摘要翻译： 一种用于在FBDIMM存储器子系统中使用可变等待时间模式来调度数据请求的服务的方法和系统。 调度算法预先计算连接到所有DRAM缓冲器芯片的数据的返回时间数据，并将返回时间数据存储在表中。 返回时间数据表示为在每个向量中一位等于“1”的一组数据返回时间二进制向量。 对于每个接收到的数据请求，存储器控制器检索适当的返回时间向量。 此外，调度算法利用表示所有执行请求的数据返回时间向量的汇编的更新历史向量，以确定接收到的请求是否对执行请求产生冲突。 通过计算和利用每个请求的分数，调度算法重新排序和调度所选择的请求的执行，以尽可能地保留尽可能多的数据总线带宽，同时避免冲突。
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公开(公告)号：US20080147996A1
公开(公告)日：2008-06-19
申请号：US12037309
申请日：2008-02-26
申请人： Steven K. Jenkins , Laura A. Weaver
发明人： Steven K. Jenkins , Laura A. Weaver
IPC分类号： G06F12/00
CPC分类号： G06F13/1652
摘要： Efficient transfer of data to and from random access memory is described. Multiple request sources and a memory system comprise memory modules having memory banks, each bank containing rows of data. The retrieval comprises transferring all data pursuant to a given request by one source before any data is transferred pursuant to a subsequent request from said second source. This retrieval is achieved using a memory arbiter that implements an algorithm for atomic read/write. Each bank is assigned a FIFO buffer by the arbiter to store access requests. The access requests are arbitrated, and an encoded value of a winner of arbitration is loaded into the relevant FIFO buffer(s) before choosing the next winner. When an encoded value reaches the head of the buffer, all associated data is accessed in the given bank before accessing data for another request source.
摘要翻译： 描述了向/从随机存取存储器的有效数据传输。 多个请求源和存储器系统包括具有存储体的存储器模块，每个存储体包含数据行。 所述检索包括在根据来自所述第二源的后续请求传送任何数据之前，根据一个源的给定请求传送所有数据。 该检索使用实现原子读/写算法的存储器仲裁器来实现。 每个存储体由仲裁器分配一个FIFO缓冲区以存储访问请求。 对访问请求进行仲裁，并且在选择下一个获胜者之前将仲裁胜者的编码值加载到相关的FIFO缓冲区中。 当编码值到达缓冲区的头部时，在访问另一个请求源的数据之前，在给定的存储体中访问所有关联的数据。
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公开(公告)号：US08547760B2
公开(公告)日：2013-10-01
申请号：US13171811
申请日：2011-06-29
IPC分类号： G11C8/18
CPC分类号： G06F3/0605 , G06F3/0659 , G06F3/0673 , G06F12/00 , G11C7/1066 , G11C7/1072 , G11C7/1093 , G11C11/40 , G11C11/40622 , G11C29/022 , G11C29/023 , G11C29/028 , G11C2207/2254 , G11C2207/2272
摘要： Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.
摘要翻译： 在双数据速率（“DDR”）系统中的存储器访问对准，包括：由存储器控制器执行对DDR存储器模块的预定地址的一个或多个写入操作，包括向DDR存储器模块发送预定量的 预定图案的数据以及数据选通信号; 由所述存储器控制器执行来自所述DDR存储器模块的预定地址的多个读取操作，包括捕获从所述DDR存储器模块发送的数据; 以及由存储器控制器根据读取操作所捕获的数据确定读取调整值和写入调整值。
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6.发明授权Structure for reducing latency associated with read operations in a memory system 失效用于减少与存储器系统中的读取操作相关联的延迟的结构公开(公告)号：US08140803B2
公开(公告)日：2012-03-20
申请号：US12114787
申请日：2008-05-04
CPC分类号： G06F13/1689
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a processor memory system, which may include a processor and a memory controller in communication with the processor through a bus. The memory controller may include a delay circuit to receive an early read indicator corresponding to read data from a memory, the delay circuit to delay the early read indicator in accordance with a pre-determined delay such that the early read indicator is passed to the bus in advance of the read data, and a delay adjustment circuit to dynamically adjust the pre-determined delay associated with the delay circuit responsive to a change in operational speed of the processor or the bus.
摘要翻译： 提供了体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构。 设计结构通常包括处理器存储器系统，其可以包括处理器和通过总线与处理器通信的存储器控制器。 存储器控制器可以包括延迟电路，用于接收对应于来自存储器的读取数据的早期读取指示符，延迟电路根据预定的延迟来延迟早期读取指示符，使得早期读取指示符被传递到总线 以及延迟调整电路，用于响应于处理器或总线的操作速度的变化来动态地调整与延迟电路相关联的预定延迟。
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公开(公告)号：US07660951B2
公开(公告)日：2010-02-09
申请号：US12037309
申请日：2008-02-26
申请人： Steven K. Jenkins , Laura A. Weaver
发明人： Steven K. Jenkins , Laura A. Weaver
IPC分类号： G06F13/00
CPC分类号： G06F13/1652
摘要： Efficient transfer of data to and from random access memory is described. Multiple request sources and a memory system comprise memory modules having memory banks, each bank containing rows of data. The retrieval comprises transferring all data pursuant to a given request by one source before any data is transferred pursuant to a subsequent request from said second source. This retrieval is achieved using a memory arbiter that implements an algorithm for atomic read/write. Each bank is assigned a FIFO buffer by the arbiter to store access requests. The access requests are arbitrated, and an encoded value of a winner of arbitration is loaded into the relevant FIFO buffer(s) before choosing the next winner. When an encoded value reaches the head of the buffer, all associated data is accessed in the given bank before accessing data for another request source.
摘要翻译： 描述了向/从随机存取存储器的有效数据传送。 多个请求源和存储器系统包括具有存储体的存储器模块，每个存储体包含数据行。 所述检索包括在根据来自所述第二源的后续请求传送任何数据之前，根据一个源的给定请求传送所有数据。 该检索使用实现原子读/写算法的存储器仲裁器来实现。 每个存储体由仲裁器分配一个FIFO缓冲区以存储访问请求。 对访问请求进行仲裁，并且在选择下一个获胜者之前将仲裁胜者的编码值加载到相关的FIFO缓冲区中。 当编码值到达缓冲区的头部时，在访问另一个请求源的数据之前，在给定的存储体中访问所有关联的数据。
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公开(公告)号：US07360035B2
公开(公告)日：2008-04-15
申请号：US10931705
申请日：2004-09-01
申请人： Steven K. Jenkins , Laura A. Weaver
发明人： Steven K. Jenkins , Laura A. Weaver
IPC分类号： G06F13/00
CPC分类号： G06F13/1652
摘要： Efficient transfer of data to and from random access memory is described. Multiple request sources and a memory system comprise memory modules having memory banks, each bank containing rows of data. The retrieval comprises transferring all data pursuant to a given request by one source before any data is transferred pursuant to a subsequent request from said second source. This retrieval is achieved using a memory arbiter that implements an algorithm for atomic read/write. Each bank is assigned a FIFO buffer by the arbiter to store access requests. The access requests are arbitrated, and an encoded value of a winner of arbitration is loaded into the relevant FIFO buffer(s) before choosing the next winner. When an encoded value reaches the head of the buffer, all associated data is accessed in the given bank before accessing data for another request source.
摘要翻译： 描述了向/从随机存取存储器的有效数据传输。 多个请求源和存储器系统包括具有存储体的存储器模块，每个存储体包含数据行。 所述检索包括在根据来自所述第二源的后续请求传送任何数据之前，根据一个源的给定请求传送所有数据。 该检索使用实现原子读/写算法的存储器仲裁器来实现。 每个存储体由仲裁器分配一个FIFO缓冲区以存储访问请求。 对访问请求进行仲裁，并且在选择下一个获胜者之前将仲裁胜者的编码值加载到相关的FIFO缓冲区中。 当编码值到达缓冲区的头部时，在访问另一个请求源的数据之前，在给定的存储体中访问所有关联的数据。
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公开(公告)号：US20090150572A1
公开(公告)日：2009-06-11
申请号：US12114792
申请日：2008-05-04
CPC分类号： G06F12/0815 , G06F2212/507
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a memory controller, memory, a bus connecting the CPU, memory controller and memory, circuitry for providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and circuitry for intermixing demand reads and speculative reads in accordance with the speculative read threshold.
摘要翻译： 提供了体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构。 该设计结构通常包括计算机系统，其包括CPU，存储器控制器，存储器，连接CPU，存储器控制器和存储器的总线，用于提供与可读取总数的所选百分比相对应的推测读取阈值的电路 推测性发布，以及根据推测读取阈值混合需求读取和推测读取的电路。
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10.发明申请STRUCTURE FOR DATA BUS BANDWIDTH SCHEDULING IN AN FBDIMM MEMORY SYSTEM OPERATING IN VARIABLE LATENCY MODE 有权在可变延迟模式下操作的FBDIMM存储器系统中的数据总线带宽调度结构公开(公告)号：US20080215783A1
公开(公告)日：2008-09-04
申请号：US12110765
申请日：2008-04-28
IPC分类号： G06F13/366 , G06F13/00 , G06F13/14 , G06F13/36
CPC分类号： G06F13/1689
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for scheduling the servicing of data requests, using the variable latency mode, in an FBDIMM memory sub-system is provided. A scheduling algorithm pre-computes return time data for data connected to DRAM buffer chips and stores the return time data in a table. The return time data is expressed as data return time binary vectors with one bit equal to “1” in each vector. For each received data request, the memory controller retrieves the appropriate return time vector. Additionally, the scheduling algorithm utilizes an updated history vector to determine whether the received request presents a conflict to the executing requests. By computing and utilizing a score for each request, the scheduling algorithm re-orders and schedules the execution of selected requests to preserve as much data bus bandwidth as possible, while avoiding conflict.
摘要翻译： 提供了一种体现在机器可读存储介质中的设计结构，用于在FBDIMM存储器子系统中使用可变延迟模式来设计，制造和/或测试用于调度数据请求的服务的设计。 调度算法预先计算连接到DRAM缓冲器芯片的数据的返回时间数据，并将返回时间数据存储在表中。 返回时间数据表示为在每个向量中一位等于“1”的数据返回时间二进制向量。 对于每个接收到的数据请求，存储器控制器检索适当的返回时间向量。 此外，调度算法利用更新的历史向量来确定接收到的请求是否对执行请求产生冲突。 通过计算和利用每个请求的分数，调度算法重新排序和调度所选择的请求的执行，以尽可能地保留尽可能多的数据总线带宽，同时避免冲突。
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