公开(公告)号：US20060129765A1

公开(公告)日：2006-06-15

申请号：US10998178

申请日：2004-11-29

申请人： Andrew Rose ,  Andrew Bolt ,  Donald Sinclair

发明人： Andrew Rose ,  Andrew Bolt ,  Donald Sinclair

IPC分类号： G06F12/00

CPC分类号： G06F11/3672

摘要： A test system, method and a computer program product are provided for testing software to be run on a data processing apparatus having a plurality of processors operable to share access to a memory system, where at least a part of the memory system has a memory ordering type which allows memory access requests at that part to be processed out of order from an original program order. The test system comprises a processor simulator for each processor of the data processing apparatus, each processor simulator being operable to execute a sequence of instructions in program order. Further, at least one access buffer unit is provided, each access buffer unit being associated with one of the processor simulators and being operable to receive memory access requests issued by that processor simulator when executing memory access instructions within the sequence of instructions. Each access buffer unit comprises at least one buffer operable to store memory access requests issued by the associated processor simulator, and a controller operable to apply an eviction policy to determine an order in which the memory access requests are output from the access buffer unit to the memory system. The eviction policy is configurable such that the memory ordering type of said part of the memory system is exercised to a degree exceeding that expected within the data processing apparatus, in order to seek to provoke an occurrence of any bug in the software resulting from an assumption of memory ordering which is not appropriate for the data processing apparatus.

摘要翻译： 提供了测试系统，方法和计算机程序产品，用于测试在具有多个处理器的数据处理装置上运行的软件，所述多个处理器可操作以共享对存储器系统的访问，其中存储器系统的至少一部分具有存储器排序 类型，允许该部分的存储器访问请求从原始程序顺序处理成不合规格。 测试系统包括用于数据处理设备的每个处理器的处理器模拟器，每个处理器模拟器可操作以以程序顺序执行指令序列。 此外，提供至少一个访问缓冲器单元，每个访问缓冲单元与处理器模拟器之一相关联，并且在执行指令序列内的存储器访问指令时可操作以接收由该处理器模拟器发出的存储器访问请求。 每个访问缓冲器单元包括至少一个缓冲器，其可操作以存储由相关联的处理器模拟器发出的存储器访问请求;以及控制器，其可操作以应用逐出策略来确定存储器访问请求从访问缓冲器单元输出到 内存系统 驱逐策略是可配置的，使得存储器系统的所述部分的存储器排序类型被执行到超过数据处理设备期望的程度，以便寻求引发由假设产生的软件中的任何错误的发生 的不适用于数据处理装置的存储器排序。