公开(公告)号：US20060129765A1

公开(公告)日：2006-06-15

申请号：US10998178

申请日：2004-11-29

申请人： Andrew Rose ,  Andrew Bolt ,  Donald Sinclair

发明人： Andrew Rose ,  Andrew Bolt ,  Donald Sinclair

IPC分类号： G06F12/00

CPC分类号： G06F11/3672

摘要： A test system, method and a computer program product are provided for testing software to be run on a data processing apparatus having a plurality of processors operable to share access to a memory system, where at least a part of the memory system has a memory ordering type which allows memory access requests at that part to be processed out of order from an original program order. The test system comprises a processor simulator for each processor of the data processing apparatus, each processor simulator being operable to execute a sequence of instructions in program order. Further, at least one access buffer unit is provided, each access buffer unit being associated with one of the processor simulators and being operable to receive memory access requests issued by that processor simulator when executing memory access instructions within the sequence of instructions. Each access buffer unit comprises at least one buffer operable to store memory access requests issued by the associated processor simulator, and a controller operable to apply an eviction policy to determine an order in which the memory access requests are output from the access buffer unit to the memory system. The eviction policy is configurable such that the memory ordering type of said part of the memory system is exercised to a degree exceeding that expected within the data processing apparatus, in order to seek to provoke an occurrence of any bug in the software resulting from an assumption of memory ordering which is not appropriate for the data processing apparatus.

摘要翻译： 提供了测试系统，方法和计算机程序产品，用于测试在具有多个处理器的数据处理装置上运行的软件，所述多个处理器可操作以共享对存储器系统的访问，其中存储器系统的至少一部分具有存储器排序 类型，允许该部分的存储器访问请求从原始程序顺序处理成不合规格。 测试系统包括用于数据处理设备的每个处理器的处理器模拟器，每个处理器模拟器可操作以以程序顺序执行指令序列。 此外，提供至少一个访问缓冲器单元，每个访问缓冲单元与处理器模拟器之一相关联，并且在执行指令序列内的存储器访问指令时可操作以接收由该处理器模拟器发出的存储器访问请求。 每个访问缓冲器单元包括至少一个缓冲器，其可操作以存储由相关联的处理器模拟器发出的存储器访问请求;以及控制器，其可操作以应用逐出策略来确定存储器访问请求从访问缓冲器单元输出到 内存系统 驱逐策略是可配置的，使得存储器系统的所述部分的存储器排序类型被执行到超过数据处理设备期望的程度，以便寻求引发由假设产生的软件中的任何错误的发生 的不适用于数据处理装置的存储器排序。

公开(公告)号：US20070208924A1

公开(公告)日：2007-09-06

申请号：US11632698

申请日：2004-07-27

申请人： Simon Ford ,  Andrew Rose

发明人： Simon Ford ,  Andrew Rose

IPC分类号： G06F9/30

CPC分类号： G06F9/30072 ,  G06F9/3001 ,  G06F9/30163

摘要： A data processing apparatus and method of handling conditional instructions in such a data processing apparatus are provided. The data processing apparatus has a pipelined processing unit for executing instructions including at least one conditional instruction from a set of conditional instructions, and a register file having a plurality of registers operable to store data values for access by the pipelined processing unit when executing the instructions. A register specified by an instruction may be either a source register holding a source data value for that instruction or a destination register into which is stored a result data value generated by execution of that instruction. The register file has a predetermined number of read ports via which data values can be read from registers of the register file. The pipelined processing unit is operable when executing the at least one conditional instruction to produce a result data value which, dependent on the existence of the condition specified by that conditional instruction, represents either the result of the computation specified by that conditional instruction or a current data value stored in the destination register for that conditional instruction. Further, each conditional instruction in the set is constrained to specify a register that is both a source register and a destination register for that conditional instruction, thereby reducing the minimum number of read ports required to support execution of that conditional instruction by the pipelined processing unit.

摘要翻译： 提供了一种在这种数据处理装置中处理条件指令的数据处理装置和方法。 数据处理装置具有流水线处理单元，用于执行包括来自一组条件指令的至少一个条件指令的指令，以及具有多个寄存器的寄存器文件，该多个寄存器可操作以在执行指令时存储由流水线处理单元进行访问的数据值 。 由指令指定的寄存器可以是保存该指令的源数据值的源寄存器或存储通过执行该指令而生成的结果数据值的目标寄存器。 寄存器文件具有预定数量的读取端口，经由该读取端口可以从寄存器文件的寄存器读取数据值。 流水线处理单元在执行至少一个条件指令以产生结果数据值时可操作，该结果数据值取决于由该条件指令指定的条件的存在表示由该条件指令指定的计算结果或当前值 存储在该条件指令的目标寄存器中的数据值。 此外，集合中的每个条件指令被限制为指定用于该条件指令的源寄存器和目的地寄存器的寄存器，由此减少支持由流水线处理单元执行该条件指令所需的读端口的最小数量 。

公开(公告)号：US20050125641A1

公开(公告)日：2005-06-09

申请号：US10889367

申请日：2004-07-13

申请人： Simon Ford ,  Dominic Symes ,  Andrew Rose ,  David Lutz ,  Christopher Hinds

发明人： Simon Ford ,  Dominic Symes ,  Andrew Rose ,  David Lutz ,  Christopher Hinds

IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/00

CPC分类号： G06F9/30167 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30145

摘要： A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements. A processor is operable to perform in parallel a data processing operation on multiple data elements accessed in at least one of the registers. Access logic is operable in response to a single access instruction to move a plurality of data elements between specified registers and a continuous block of memory in which data elements are stored as an array of structures having a structure format, the structure format having a plurality of components. The single access instruction identifies the number of components in the structure format, and the access logic is further operable to rearrange the plurality of data elements as they are moved such that each specified register stores data elements of one component whilst in memory the data elements are stored as the array of structures.

摘要翻译： 提供了一种用于在寄存器和存储器之间移动数据的数据处理装置和方法。 数据处理装置包括具有可操作以存储数据元素的多个寄存器的寄存器数据存储器。 处理器可操作以对在至少一个寄存器中访问的多个数据元素并行地执行数据处理操作。 访问逻辑可操作以响应于单个访问指令来移动指定寄存器之间的多个数据元素和其中数据元素被存储为具有结构格式的结构的阵列的连续存储块，所述结构格式具有多个 组件。 单个访问指令标识结构格式的组件的数量，并且访问逻辑还可用于在移动多个数据元素时重新排列多个数据元素，使得每个指定的寄存器存储一个组件的数据元素，而在存储器中数据元素是 存储为结构数组。

公开(公告)号：US20050125636A1

公开(公告)日：2005-06-09

申请号：US10889316

申请日：2004-07-13

申请人： Simon Ford ,  Dominic Symes ,  Daniel Kershaw ,  Andrew Rose

发明人： Simon Ford ,  Dominic Symes ,  Daniel Kershaw ,  Andrew Rose

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/315 ,  G06F15/00 ,  G06F15/80 ,  G06F17/16

CPC分类号： G06F9/3013 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30138 ,  G06F9/3887

摘要： A data processing apparatus is disclosed. The apparatus comprises a register data store comprising a plurality of registers. The apparatus further comprises a data processor operable to perform in parallel a data processing operation on data elements; and decode logic responsive to a single vector-by-scalar instruction to control the data processor so as to specify one of the plurality of registers as a first source register operable to store a plurality of source data elements, to specify another of the plurality of registers as a second source register operable to store a plurality of selectable data elements, to select one of said selectable data elements as a scalar operand and to perform a vector-by-scalar operation in parallel on the source data elements, each vector-by-scalar operation causing a resultant data element to be generated from a source data element and the scalar operand. By providing a source register which contains selectable data elements it is possible to select one of those data elements as a scalar operand and to perform multiple vector-by-scalar operations in parallel using the same scalar operand on all source data elements.

摘要翻译： 公开了一种数据处理装置。 该装置包括一个包括多个寄存器的寄存器数据存储器。 该装置还包括数据处理器，可操作以并行地执行数据元素的数据处理操作; 以及响应于单个逐标量指令来解码逻辑以控制所述数据处理器，以便将所述多个寄存器中的一个指定为可操作以存储多个源数据元素的第一源寄存器，以指定所述多个 寄存器作为可操作以存储多个可选择数据元素的第二源寄存器，将所述可选数据元素中的一个选择为标量操作数，并且对源数据元素并行执行逐标量运算，每个向量 - 标量操作，使得从源数据元素和标量操作数生成结果数据元素。 通过提供包含可选数据元素的源寄存器，可以选择这些数据元素中的一个作为标量操作数，并且使用所有源数据元素上的相同标量操作数并行地执行多个逐标量操作。

公开(公告)号：US20060144871A1

公开(公告)日：2006-07-06

申请号：US11296131

申请日：2005-12-07

申请人： Michael Van Tuyl ,  James Chiao ,  Michael Herrmann ,  Andrew Rose

发明人： Michael Van Tuyl ,  James Chiao ,  Michael Herrmann ,  Andrew Rose

IPC分类号： B65D47/18 ,  G01N29/024 ,  G01N29/028 ,  G01N29/032

CPC分类号： G01N29/343 ,  G01N9/24 ,  G01N11/10 ,  G01N29/024 ,  G01N29/028 ,  G01N29/032 ,  G01N29/221 ,  G01N29/222 ,  G01N2291/02809 ,  G01N2291/02818 ,  G01N2291/02836 ,  G01N2291/02881 ,  G01N2291/044

摘要： A liquid dispensing apparatus for dispensing droplets of a liquid, and methods for measuring various fluid parameters of the liquid are described. The liquid dispensing apparatus comprises a container having a chamber for holding a liquid. An orifice is positioned at an end of the chamber for dispensing droplets of the liquid, the orifice being configured to retain the liquid in the container if the container is positioned with the orifice facing in a downward direction. An acoustic transducer means is at least partially positioned in the chamber for periodically propagating a focused acoustic beam toward the orifice and through at least some of the liquid while the liquid is contained in the chamber, with the focused acoustic beam being capable of causing a droplet of the liquid to be ejected from the orifice when a free surface of the liquid is within the depth of field of the acoustic transducer means. Fluid parameters that can be measured include the sound velocity in the liquid, liquid level and liquid concentration, liquid acoustic impedance, liquid density and ultrasonic viscosity.

摘要翻译： 描述了用于分配液体的液滴的液体分配装置以及用于测量液体的各种流体参数的方法。 液体分配装置包括具有用于保持液体的室的容器。 孔口位于腔室的端部，用于分配液体的液滴，如果容器定位成孔口朝向下方的方向，孔口被配置成将液体保持在容器中。 声学换能器装置至少部分地定位在腔室中，用于在聚焦的声束能够引起液滴时，将聚焦的声束周期性地传播到孔口并通过至少一些液体，同时液体被容纳在腔室中 当液体的自由表面在声换能器装置的深度范围内时，从喷嘴喷射的液体。 可以测量的流体参数包括液体中的声速，液位和液体浓度，液体声阻抗，液体密度和超声波粘度。

公开(公告)号：US20050167920A1

公开(公告)日：2005-08-04

申请号：US10708033

申请日：2004-02-04

申请人： Jed Rose ,  Frederique Behm ,  Justin Rose ,  Andrew Rose ,  Anthony Rose

发明人： Jed Rose ,  Frederique Behm ,  Justin Rose ,  Andrew Rose ,  Anthony Rose

IPC分类号： A63F1/00 ,  A63F1/04 ,  A63F3/04

CPC分类号： A63F1/04 ,  A63F3/04 ,  A63F2001/0475

摘要： Playing cards having a deck divided into a first suit of threat cards and a second suit of tool cards. Play is conducted by each player concocting a story based on the cards, for instance, a defense, using what is shown on the tool card or cards the player has, against the threat shown on the threat card the player has. Points may be awarded for creativity in telling a story with the winner having the most points at the end of play, or alternatively, players may play for the fun of creating stories.

摘要翻译： 具有甲板的纸牌分为第一套威胁卡和第二套工具卡。 玩家是由每个玩家根据卡片进行的故事进行的，例如，使用玩家所拥有的工具卡或卡上显示的内容来抵御玩家所拥有的威胁卡上的威胁。 点击奖励可以在玩家的最后得分最高的玩家讲故事时给予创造力，或者玩家可以玩创造故事的乐趣。

公开(公告)号：US20050125640A1

公开(公告)日：2005-06-09

申请号：US10889318

申请日：2004-07-13

申请人： Simon Ford ,  Dominic Symes ,  Andrew Rose ,  David Lutz ,  Christopher Hinds

发明人： Simon Ford ,  Dominic Symes ,  Andrew Rose ,  David Lutz ,  Christopher Hinds

IPC分类号： G06F9/00 ,  G06F9/30 ,  G06F9/312 ,  G06F9/315 ,  G06F9/345 ,  G06F9/38 ,  G06F15/80

CPC分类号： G06F9/3887 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30138 ,  G06F9/3822 ,  G06F9/3885

摘要： A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements. A processor is operable to perform in parallel a data processing operation on multiple data elements occupying different lanes of parallel processing in at least one of the registers. Access logic is provided which is responsive to a single access instruction to move a plurality of data elements between a chosen one of the lanes in specified registers and a structure within memory having a structure format, the structure format having a plurality of components. The single access instruction identifies the number of components in the structure format, and the access logic is operation to arrange the plurality of data elements as they are moved such that data elements of different components are stored in different specified registers within the chosen lane whilst in memory the data elements are stored as the structure.

摘要翻译： 提供了一种用于在寄存器和存储器之间移动数据的数据处理装置和方法。 数据处理装置包括具有可操作以存储数据元素的多个寄存器的寄存器数据存储器。 处理器可操作以并行地执行对至少一个寄存器中的并行处理的不同通道的多个数据元素的数据处理操作。 提供了访问逻辑，其响应于单个访问指令，以在指定寄存器中的所选择的一个通道中移动多个数据元素，以及在具有结构格式的存储器内的结构，所述结构格式具有多个组件。 单个访问指令标识结构格式中的组件的数量，并且访问逻辑是在移动多个数据元素时排列多个数据元素的操作，使得不同组件的数据元素存储在所选择的通道内的不同指定的寄存器中，同时 存储数据元素作为结构存储。

公开(公告)号：US20070150771A1

公开(公告)日：2007-06-28

申请号：US11314737

申请日：2005-12-22

申请人： Antony Penton ,  Vladimir Vasekin ,  Andrew Rose ,  Paul Hughes ,  Christopher Wrigley

发明人： Antony Penton ,  Vladimir Vasekin ,  Andrew Rose ,  Paul Hughes ,  Christopher Wrigley

IPC分类号： G06F1/12

CPC分类号： G06F1/12

摘要： A data processing apparatus comprising a plurality of data processors, each data processor comprising: first logic operable in a first clock domain and further logic operable in a second clock domain, said first and second clock domains being asynchronous with each other; a synchroniser operable to synchronise a signal processed by said first logic to produce a signal synchronised to said second clock domain; a synchronised signal output operable to export from said data processor said synchronised signal output from said synchroniser; and a signal input operable to import a signal to said data processor, said data processor being operable to route said imported signal to said further logic; wherein said plurality of data processors are arranged to operate in parallel with each other and said data processing apparatus further comprises: combining logic arranged to receive said exported synchronised signals from each of said plurality of data processors and to combine said exported synchronised signals to produce a resultant signal, said resultant signal being routed to each of said signal inputs of said plurality of data processors.

摘要翻译： 一种包括多个数据处理器的数据处理装置，每个数据处理器包括：可在第一时钟域中操作的第一逻辑和可在第二时钟域中操作的另外的逻辑，所述第一和第二时钟域彼此异步; 同步器，其可操作以使由所述第一逻辑处理的信号同步，以产生与所述第二时钟域同步的信号; 同步信号输出可操作以从所述数据处理器输出从所述同步器输出的所述同步信号; 以及可操作以将信号导入所述数据处理器的信号输入，所述数据处理器可操作以将所述导入的信号路由到所述另外的逻辑; 其中所述多个数据处理器被布置为彼此并行操作，并且所述数据处理装置还包括：组合逻辑，被布置为从所述多个数据处理器中的每一个接收所述输出的同步信号，并组合所述输出的同步信号以产生 所述结果信号被路由到所述多个数据处理器的每个所述信号输入端。

公开(公告)号：US20050283593A1

公开(公告)日：2005-12-22

申请号：US10870548

申请日：2004-06-18

申请人： Vladimir Vasekin ,  Andrew Rose ,  Stuart Biles

发明人： Vladimir Vasekin ,  Andrew Rose ,  Stuart Biles

IPC分类号： G06F9/00 ,  G06F9/38

CPC分类号： G06F9/3848

摘要： A branch prediction mechanism within a pipelined processing apparatus uses a history value HV which records preceding branch outcomes in either a first mode or a second mode. In the first mode respective bits within the history value represent a mixture of branch taken and branch not taken outcomes. In the second mode a count value within the history value indicates a count of a contiguous sequence of branch taken outcomes.

摘要翻译： 流水线处理装置内的分支预测机构使用历史值HV，其以第一模式或第二模式记录先前分支结果。 在第一个模式中，历史值中的各个位表示分支取和分支未采取结果的混合。 在第二模式中，历史值内的计数值表示分支采取结果的连续序列的计数。

公开(公告)号：US20050216711A1

公开(公告)日：2005-09-29

申请号：US10807498

申请日：2004-03-24

申请人： David Butcher ,  Stephen Hill ,  Hedley Francis ,  Vladimir Vasekin ,  Andrew Rose

发明人： David Butcher ,  Stephen Hill ,  Hedley Francis ,  Vladimir Vasekin ,  Andrew Rose

IPC分类号： G06F9/00 ,  G06F9/318 ,  G06F9/355 ,  G06F9/38

CPC分类号： G06F9/3861 ,  G06F9/30174 ,  G06F9/355

摘要： A processor 6 is provided with an instruction decoder 18 which is responsive to memory access instructions to determine whether the base register value being used matches a null value and if such a match occurs then branches to a null value exception handler.

摘要翻译： 处理器6设置有指令解码器18，该指令解码器18响应于存储器访问指令来确定正在使用的基本寄存器值是否与空值匹配，并且如果发生这样的匹配，则分支到空值异常处理程序。