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1.发明授权System, method and computer program product for equivalence checking between designs with sequential differences 有权用于在具有连续差异的设计之间进行等价检查的系统，方法和计算机程序产品公开(公告)号：US07350168B1
公开(公告)日：2008-03-25
申请号：US11129238
申请日：2005-05-12
申请人： Anmol Mathur , Nikhil Sharma , Deepak Goyal , Gagan Hasteer , Rajarshi Mukherjee
发明人： Anmol Mathur , Nikhil Sharma , Deepak Goyal , Gagan Hasteer , Rajarshi Mukherjee
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A system, method and computer program product are provided for equivalency checking between a first design and a second design having sequential differences. To accomplish the equivalency checking, sequential differences between a first design and a second design are identified. It is then determined whether the first design and the second design are equivalent, utilizing the identified sequential differences.
摘要翻译： 提供了一种系统，方法和计算机程序产品，用于在具有顺序差异的第一设计和第二设计之间进行等同性检查。 为了完成等效性检查，识别第一设计和第二设计之间的顺序差异。 然后，使用所识别的顺序差，确定第一设计和第二设计是否等同。
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2.发明授权Method and system for inplace symbolic simulation over multiple cycles of a multi-clock domain design 失效用于在多时钟域设计的多个周期上进行符号仿真的方法和系统公开(公告)号：US07284218B1
公开(公告)日：2007-10-16
申请号：US11084778
申请日：2005-03-18
申请人： Sumit Roy , Gagan Hasteer , Anmol Mathur
发明人： Sumit Roy , Gagan Hasteer , Anmol Mathur
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method and a system for inplace symbolic simulation of circuits. This method is applicable to both single clock and multiple clock domain designs. The method performs inplace symbolic simulation by appending slots to the various objects of the circuit. The slot associated with an object is a function of time, and it represents the functionality of the element at a given time. The method comprises the steps of determining a phase-list, determining ticks associated with each object of the circuit. Based on these ticks, slots are generated. Further, relations between the slots of the various objects of the circuit are captured.
摘要翻译： 一种用于电路的现场符号仿真的方法和系统。 该方法适用于单时钟和多时钟域设计。 该方法通过将插槽附加到电路的各种对象来进行内部符号仿真。 与对象关联的时隙是时间的函数，它表示给定时间的元素的功能。 该方法包括以下步骤：确定相位列表，确定与电路的每个对象相关联的刻度。 基于这些刻度，生成插槽。 此外，捕获电路的各个对象的时隙之间的关系。
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3.发明授权System, method, and computer program product for determining equivalence of netlists utilizing at least one transformation 有权用于使用至少一个变换来确定网表的等价性的系统，方法和计算机程序产品公开(公告)号：US08122401B1
公开(公告)日：2012-02-21
申请号：US12260837
申请日：2008-10-29
申请人： Pankaj P. Chauhan , Deepak Goyal , Anmol Mathur
发明人： Pankaj P. Chauhan , Deepak Goyal , Anmol Mathur
CPC分类号： G06F17/504
摘要： A system, method and computer program product are provided for determining equivalence of netlists utilizing at least one transformation. In use, a netlist including a plurality of infinite portions and a plurality of finite portions is identified. Additionally, at least some of the finite portions are transformed, utilizing at least one predetermined transformation. Further, an equivalence of the netlist and another netlist is determined, utilizing at least a subset of the finite portions and the infinite portions. Moreover, the transformation identifies a word-level functionality of the at least some of the finite portions by converting bit-level functionality into word-level functionality.
摘要翻译： 提供了一种系统，方法和计算机程序产品，用于使用至少一个变换来确定网表的等同性。 在使用中，识别包括多个无限部分和多个有限部分的网表。 另外，使用至少一个预定变换来转换至少一些有限部分。 此外，利用有限部分和无限部分的至少一个子集来确定网表和另一网表的等价物。 此外，转换通过将位级功能转换为字级功能来识别至少一些有限部分的字级功能。
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4.发明授权System, method, and computer program product for determining equivalence of netlists utilizing abstractions and transformations 有权系统，方法和计算机程序产品，用于确定使用抽象和转换的网表的等价性公开(公告)号：US08117571B1
公开(公告)日：2012-02-14
申请号：US12260851
申请日：2008-10-29
申请人： Pankaj P. Chauhan , Deepak Goyal , Anmol Mathur
发明人： Pankaj P. Chauhan , Deepak Goyal , Anmol Mathur
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A system, method and computer program product are provided for determining equivalence of netlists utilizing at least one transformation. In use, a netlist including a plurality of infinite portions and a plurality of finite portions is identified. Additionally, at least some of the finite portions are transformed, utilizing at least one predetermined transformation. Further, an equivalence of the netlist and another netlist is determined, utilizing at least a subset of the finite portions and the infinite portions. Moreover, an abstraction is performed on the netlist.
摘要翻译： 提供了一种系统，方法和计算机程序产品，用于使用至少一个变换来确定网表的等同性。 在使用中，识别包括多个无限部分和多个有限部分的网表。 另外，使用至少一个预定变换来转换至少一些有限部分。 此外，利用有限部分和无限部分的至少一个子集来确定网表和另一网表的等价物。 此外，在网表上执行抽象。
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公开(公告)号：US07222317B1
公开(公告)日：2007-05-22
申请号：US10822166
申请日：2004-04-09
申请人： Anmol Mathur , Deepak Goyal
发明人： Anmol Mathur , Deepak Goyal
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F17/509
摘要： The present invention discloses a method and system for computer-aided circuit design for checking the equivalence of data flow graphs by splitting data flow graphs representing finite precision arithmetic circuits into lossless subgraphs representing infinite-precision arithmetic circuits, and edges with information loss. The set of lossless subgraphs generated are leveled, and checked for equivalence as expressions. The edges with information loss are compared by establishing the equivalence of their bit width. The present invention declares data flow graphs as equal, if the respective lossless subgraphs and the bit-width at the corresponding edges with information loss are equal.
摘要翻译： 本发明公开了一种用于计算机辅助电路设计的方法和系统，用于通过将表示有限精密算术电路的数据流图分解成表示无限精度运算电路的无损子图和具有信息丢失的边来检查数据流图的等效性。 生成的无损子图的集合被平整，并且检查等价作为表达式。 通过确定其位宽的等价性来比较具有信息丢失的边。 如果各个无损子图和具有信息丢失的相应边缘的位宽相等，则本发明声明数据流图相同。
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6.发明授权Enhancing mergeability of datapaths and reducing datapath widths responsively to required precision 有权提高数据路径的可合并性，并根据需要的精度减少数据路径宽度公开(公告)号：US06772399B2
公开(公告)日：2004-08-03
申请号：US10173477
申请日：2002-06-17
申请人： Sanjeev Saluja , Anmol Mathur
发明人： Sanjeev Saluja , Anmol Mathur
IPC分类号： G06F1750
CPC分类号： G06F8/443 , G06F9/44 , G06F17/5045
摘要： A practical definition for determining a required precision is provided and used to reduce the widths of operators and edges of data flow graphs. A bottom-up procedure for systematically pruning data flow graphs is described. The result is shown to enhance the mergeability of subgraphs and provide reduced data path widths. This may result in lower area, power requirements and other benefits as readily understood in the field of circuit design.
摘要翻译： 提供用于确定所需精度的实际定义，并用于减少数据流图的运算符和边缘的宽度。 描述了用于系统地修剪数据流图的自下而上的过程。 结果显示为增强子图的合并性并提供减少的数据路径宽度。 这可能导致在电路设计领域中容易理解的较低的面积，功率要求和其他益处。
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7.发明授权System, method and computer program product for word-level operator-to-cell mapping 有权用于字级操作员到单元格映射的系统，方法和计算机程序产品公开(公告)号：US07673257B1
公开(公告)日：2010-03-02
申请号：US11682243
申请日：2007-03-05
申请人： Shail Bains , Abhishek Ranjan , Anmol Mathur , Venky Ramachandran
发明人： Shail Bains , Abhishek Ranjan , Anmol Mathur , Venky Ramachandran
IPC分类号： G06F17/50
CPC分类号： G06F7/5443 , G06F7/53
摘要： A mapping system, method and computer program product are provided. In use, at least one arithmetic operator is received. Further, the at least one arithmetic operator is mapped to at least one cell, at a word-level.
摘要翻译： 提供了映射系统，方法和计算机程序产品。 在使用中，接收至少一个算术运算符。 此外，至少一个算术运算符在字级被映射到至少一个单元。
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8.发明授权公开(公告)号：US09720859B1
公开(公告)日：2017-08-01
申请号：US12772051
申请日：2010-04-30
申请人： Nikhil Tripathi , Venky Ramachandran , Malay Haldar , Sumit Roy , Anmol Mathur , Abhishek Roy , Mohit Kumar
发明人： Nikhil Tripathi , Venky Ramachandran , Malay Haldar , Sumit Roy , Anmol Mathur , Abhishek Roy , Mohit Kumar
CPC分类号： G06F13/1626 , G06F3/0628
摘要： A system, method and computer program product are provided for conditionally eliminating a memory read request. In use, a memory read request is identified. Additionally, it is determined whether the memory read request is an unnecessary memory read request. Further, the memory read request is conditionally eliminated, based on the determination.
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公开(公告)号：US06832357B2
公开(公告)日：2004-12-14
申请号：US10173066
申请日：2002-06-17
申请人： Sanjeev Saluja , Anmol Mathur
发明人： Sanjeev Saluja , Anmol Mathur
IPC分类号： G06F1750
CPC分类号： G06F8/443 , G06F9/44 , G06F17/5045
摘要： A Huffman algorithm is applied to revise the topology of a data flow graph. The result of the application of the algorithm is an increase in the sizes of at least some clusters (i.e., enhanced mergeability). The Huffman rebalancing of the topology may also result in the benefit of allowing further pruning of the bitwidths of data flow paths, which may further enhance mergeability. Thus, the algorithm may be applied with a maximum information content analysis.
摘要翻译： 应用霍夫曼算法来修改数据流图的拓扑。 应用该算法的结果是至少一些簇的大小增加（即，增强的合并性）。 拓扑的霍夫曼重新平衡还可以带来进一步修剪数据流路径的位宽度的好处，这可能进一步增强可合并性。 因此，该算法可以应用于最大信息内容分析。
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10.发明授权公开(公告)号：US06772398B2
公开(公告)日：2004-08-03
申请号：US10173338
申请日：2002-06-17
申请人： Sanjeev Saluja , Anmol Mathur
发明人： Sanjeev Saluja , Anmol Mathur
IPC分类号： G06F1750
CPC分类号： G06F8/443 , G06F9/44 , G06F17/5045
摘要： A practical definition for determining an upper bound on information content is provided and used to reduce the widths of operators and edges of data flow graphs. A top down procedure for systematically pruning data flow graphs is described. The result is shown to enhance the mergeability of subgraphs and provide reduced data path widths. This may result in lower area, power requirements and other benefits as readily understood in the field of circuit design.
摘要翻译： 提供了确定信息内容上界的实际定义，并用于减少数据流图的运算符和边缘的宽度。 描述了自动修剪数据流图的自上而下的过程。 结果显示为增强子图的合并性并提供减少的数据路径宽度。 这可能导致在电路设计领域中容易理解的较低的面积，功率要求和其他益处。
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