公开(公告)号：US07487487B1

公开(公告)日：2009-02-03

申请号：US12060488

申请日：2008-04-01

申请人： Anthony D. Polson ,  David Lackey ,  Theodoros E. Anemikos ,  Laura Chadwick

发明人： Anthony D. Polson ,  David Lackey ,  Theodoros E. Anemikos ,  Laura Chadwick

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： A design structure for monitoring of the performance of semiconductor circuits, such as circuit delay, across a chip. The design structure may include a clock source and a plurality of process monitors. The design structure may be used to construct a “schmoo plot” by varying a frequency of the clock source to determine the delay of process monitors at various locations across the chip.

摘要翻译： 一种用于监控半导体电路性能的设计结构，例如芯片上的电路延迟。 该设计结构可以包括时钟源和多个处理监视器。 设计结构可用于通过改变时钟源的频率来构建“schmoo图”，以确定芯片上各处的处理监视器的延迟。

公开(公告)号：US20050088888A1

公开(公告)日：2005-04-28

申请号：US10994496

申请日：2004-11-22

申请人： Laura Chadwick ,  William Corbin ,  Jeffrey Dreibelbis ,  Erik Nelson ,  Thomas Obremski ,  Toshiharu Saitoh ,  Donald Wheater

发明人： Laura Chadwick ,  William Corbin ,  Jeffrey Dreibelbis ,  Erik Nelson ,  Thomas Obremski ,  Toshiharu Saitoh ,  Donald Wheater

IPC分类号： G11C29/26 ,  G11C7/00

CPC分类号： G11C29/12015 ,  G11C11/401 ,  G11C29/26 ,  G11C2207/104

摘要： A method and system for testing a DRAM comprised of DRAM blocks. The method comprises: in a processor based built-in self test system, generating a test data pattern; for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block; wherein for each DRAM block, the performing the write of the test pattern into the DRAM block is performed before the performing the pause for the predetermined period of time, and the performing the read of the resulting data pattern from the DRAM block is performed after the performing the pause for the predetermined period of time; and wherein at least a portion of the pause for the predetermined period of time of two or more the DRAM blocks overlap in time.

摘要翻译： 一种用于测试由DRAM块组成的DRAM的方法和系统。 该方法包括：在基于处理器的内置自检系统中，生成测试数据模式; 对于每个DRAM块，执行将测试数据模式写入DRAM块，执行预定时间段的暂停，以及从DRAM块执行结果数据模式的读取; 对于每个DRAM块，在执行暂停预定时间段之前执行将测试图案写入DRAM块的执行，并且在所述DRAM块之后执行所得到的数据模式的读取在 执行暂停预定时间段; 并且其中DRAM块的两个或更多个的预定时间段的暂停的至少一部分在时间上重叠。