公开(公告)号：US20050088888A1

公开(公告)日：2005-04-28

申请号：US10994496

申请日：2004-11-22

申请人： Laura Chadwick ,  William Corbin ,  Jeffrey Dreibelbis ,  Erik Nelson ,  Thomas Obremski ,  Toshiharu Saitoh ,  Donald Wheater

发明人： Laura Chadwick ,  William Corbin ,  Jeffrey Dreibelbis ,  Erik Nelson ,  Thomas Obremski ,  Toshiharu Saitoh ,  Donald Wheater

IPC分类号： G11C29/26 ,  G11C7/00

CPC分类号： G11C29/12015 ,  G11C11/401 ,  G11C29/26 ,  G11C2207/104

摘要： A method and system for testing a DRAM comprised of DRAM blocks. The method comprises: in a processor based built-in self test system, generating a test data pattern; for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block; wherein for each DRAM block, the performing the write of the test pattern into the DRAM block is performed before the performing the pause for the predetermined period of time, and the performing the read of the resulting data pattern from the DRAM block is performed after the performing the pause for the predetermined period of time; and wherein at least a portion of the pause for the predetermined period of time of two or more the DRAM blocks overlap in time.

摘要翻译： 一种用于测试由DRAM块组成的DRAM的方法和系统。 该方法包括：在基于处理器的内置自检系统中，生成测试数据模式; 对于每个DRAM块，执行将测试数据模式写入DRAM块，执行预定时间段的暂停，以及从DRAM块执行结果数据模式的读取; 对于每个DRAM块，在执行暂停预定时间段之前执行将测试图案写入DRAM块的执行，并且在所述DRAM块之后执行所得到的数据模式的读取在 执行暂停预定时间段; 并且其中DRAM块的两个或更多个的预定时间段的暂停的至少一部分在时间上重叠。

公开(公告)号：US20050172194A1

公开(公告)日：2005-08-04

申请号：US10707971

申请日：2004-01-29

申请人： Jeffrey Dreibelbis ,  Kevin Gorman ,  Michael Nelms

发明人： Jeffrey Dreibelbis ,  Kevin Gorman ,  Michael Nelms

IPC分类号： G01R31/28 ,  G01R31/317 ,  G11C29/00 ,  G11C29/14 ,  G11C29/16 ,  G11C29/44

CPC分类号： G11C29/14 ,  G01R31/31724 ,  G01R31/3187 ,  G11C29/16 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/72 ,  G11C2029/0401

摘要： Disclosed is a hybrid built-in self test (BIST) architecture for embedded memory arrays that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A standalone BIST logic controller operates at a lower frequency and communicates with a plurality of embedded memory arrays using a BIST instruction set. A block of higher-speed test logic is incorporated into each embedded memory array under test and locally processes BIST instructions received from the standalone BIST logic controller at a higher frequency. The higher-speed test logic includes a multiplier for increasing the frequency of the BIST instructions from the lower frequency to the higher frequency. The standalone BIST logic controller enables a plurality of higher-speed test logic structures in a plurality of embedded memory arrays.

摘要翻译： 公开了一种用于嵌入式存储器阵列的混合内置自测（BIST）架构，其将BIST功能分段成远程低速可执行指令和本地较高速可执行指令。 独立的BIST逻辑控制器以较低的频率工作，并使用BIST指令集与多个嵌入式存储器阵列进行通信。 一个高速测试逻辑块被并入被测试的每个嵌入式存储器阵列中，并以更高的频率在本地处理从独立BIST逻辑控制器接收的BIST指令。 高速测试逻辑包括用于将BIST指令的频率从较低频率增加到较高频率的乘法器。 独立的BIST逻辑控制器使多个嵌入式存储器阵列中的多个更高速的测试逻辑结构能够实现。