公开(公告)号：US09317284B2

公开(公告)日：2016-04-19

申请号：US14034658

申请日：2013-09-24

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion ,  Alexander C. Klaiber

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30021 ,  G06F9/3004 ,  G06F9/3838

Abstract: In an embodiment, a processor may implement a vector hazard check instruction to detect dependencies between vector memory operations based on the addresses of the vectors accessed by the vector memory operations. The addresses may be specified via a base address and a vector of indexes for each vector. In an embodiment, one of the base addresses may be an implied (or assumed) zero address, reducing the number of operands of the hazard check instruction.

Abstract translation: 在一个实施例中，处理器可以实施向量危险检查指令，以基于由向量存储器操作所访问的向量的地址来检测向量存储器操作之间的依赖性。 可以通过基地址和每个向量的索引向量来指定地址。 在一个实施例中，基地址之一可以是隐含（或假设的）零地址，减少了危险检查指令的操作数。

公开(公告)号：US20160092217A1

公开(公告)日：2016-03-31

申请号：US14704396

申请日：2015-05-05

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion ,  Charles E. Tucker ,  Alexander C. Klaiber

IPC: G06F9/30

CPC classification number: G06F9/30021 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/3013 ,  G06F9/325

Abstract: In an embodiment, a processor may implement a vector instruction set including one or more compare break instructions. The compare break instruction may take a pair of operands which may be compared to determine loop termination conditions, and may output a predicate vector indicating which vector elements correspond to loop iterations that are executed and which vector elements correspond to loop iterations that are not executed. The predicate vector may serve as a predicate to vector instructions forming the body of the loop, correctly executing the specified number of iterations. The compare break instruction may be coded to check for a variety of conditions (e.g. equal, not equal, greater than, less than, etc.). In an embodiment, the compare break instruction may take a predicate operand as well, which may be combined with the predicate vector produced by the comparison operations to produce the output vector.

Abstract translation: 在一个实施例中，处理器可以实现包括一个或多个比较中断指令的向量指令集。 比较中断指令可以采用一对可以与确定循环终止条件进行比较的操作数，并且可以输出指示哪些向量元素对应于执行的循环迭代的谓词向量，哪些向量元素对应于不执行的循环迭代。 谓词向量可以作为形成循环体的向量指令的谓词，正确执行指定数量的迭代。 比较中断指令可以被编码以检查各种条件（例如相等，不等于，大于，小于等）。 在一个实施例中，比较中断指令也可以采用谓词操作数，其可以与由比较操作产生的谓词向量组合以产生输出向量。

公开(公告)号：US20160092398A1

公开(公告)日：2016-03-31

申请号：US14704421

申请日：2015-05-05

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion ,  Charles E. Tucker ,  Alexander C. Klaiber

IPC: G06F15/80 ,  G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/3013 ,  G06F9/3838

Abstract: In an embodiment, a processor may implement a vector instruction set including a conditional termination instruction (CTerm). The CTerm instruction may take two source operands and compare them according to a specified condition, updating flags as a result of the instruction. The flags may be used to affect predicate vector generation to control vectorized loop execution. In an embodiment, the vector instruction set may also include a conditional termination predicate instruction (CTPred). The CTPred instruction may take a pair of predicate vectors and a set of flags as operands, and may generate: a predicate vector to control parallel processing of vector elements, and a set of flags to control further loop processing. Either instruction may be used to efficiently manage vector loops in various embodiments, or the instructions may be used together.

Abstract translation: 在一个实施例中，处理器可以实现包括条件终止指令（CTerm）的向量指令集。 CTerm指令可以采用两个源操作数，并根据指定的条件进行比较，作为指令的结果更新标志。 标志可用于影响谓词向量生成以控制向量化循环执行。 在一个实施例中，向量指令集还可以包括条件终止谓词指令（CTPred）。 CTPred指令可以采用一对谓词向量和一组标志作为操作数，并且可以生成：用于控制向量元素的并行处理的谓词向量，以及用于控制进一步的循环处理的一组标志。 在各种实施例中可以使用任一指令来有效地管理向量循环，或者可以一起使用指令。

公开(公告)号：US20150089188A1

公开(公告)日：2015-03-26

申请号：US14034658

申请日：2013-09-24

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion ,  Alexander C. Klaiber

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30021 ,  G06F9/3004 ,  G06F9/3838

Abstract: In an embodiment, a processor may implement a vector hazard check instruction to detect dependencies between vector memory operations based on the addresses of the vectors accessed by the vector memory operations. The addresses may be specified via a base address and a vector of indexes for each vector. In an embodiment, one of the base addresses may be an implied (or assumed) zero address, reducing the number of operands of the hazard check instruction.

Abstract translation: 在一个实施例中，处理器可以实施向量危险检查指令，以基于由向量存储器操作所访问的向量的地址来检测向量存储器操作之间的依赖性。 可以通过基地址和每个向量的索引向量来指定地址。 在一个实施例中，基地址之一可以是隐含（或假设的）零地址，减少了危险检查指令的操作数。