公开(公告)号：US11947462B1

公开(公告)日：2024-04-02

申请号：US17653418

申请日：2022-03-03

Applicant: Apple Inc.

Inventor： Yoong Chert Foo ,  Terence M. Potter ,  Donald R. DeSota ,  Benjiman L. Goodman ,  Aroun Demeure ,  Cheng Li ,  Winnie W. Yeung

IPC: G06F12/08 ,  G06F12/0875

CPC classification number: G06F12/0875 ,  G06F2212/60

Abstract: Techniques are disclosed relating to cache footprint management. In some embodiments, execution circuitry is configured to perform operations for instructions from multiple threads in parallel. Cache circuitry may store information operated on by threads executed by the execution circuitry. Scheduling circuitry may arbitrate among threads to schedule threads for execution by the execution circuitry. Tracking circuitry may determine one or more performance metrics for the cache circuitry. Control circuitry may, based on the one or more performance metrics meeting a threshold, reduce a limit on a number of threads considered for arbitration by the scheduling circuitry, to control a footprint of information stored by the cache circuitry. Disclosed techniques may advantageously reduce or avoid cache thrashing for certain processor workloads.