公开(公告)号：US20240045808A1

公开(公告)日：2024-02-08

申请号：US18490588

申请日：2023-10-19

Applicant: Apple Inc.

Inventor： Justin A. Hensley ,  Karl D. Mann ,  Yoong Chert Foo ,  Terence M. Potter ,  Frank W. Liljeros ,  Ralph C. Taylor

IPC: G06F12/1018 ,  G06F12/084

CPC classification number: G06F12/1018 ,  G06F12/084 ,  G06F30/392

Abstract: Techniques are disclosed relating to dynamically allocating and mapping private memory for requesting circuitry. Disclosed circuitry may receive a private address and translate the private address to a virtual address (which an MMU may then translate to physical address to actually access a storage element). In some embodiments, private memory allocation circuitry is configured to generate page table information and map private memory pages for requests if the page table information is not already setup. In various embodiments, this may advantageously allow dynamic private memory allocation, e.g., to efficiently allocate memory for graphics shaders with different types of workloads. Disclosed caching techniques for page table information may improve performance relative to traditional techniques. Further, disclosed embodiments may facilitate memory consolidation across a device such as a graphics processor.

公开(公告)号：US11645084B2

公开(公告)日：2023-05-09

申请号：US17470682

申请日：2021-09-09

Applicant: Apple Inc.

Inventor： Christopher A. Burns ,  Liang-Kai Wang ,  Robert D. Kenney ,  Terence M. Potter

IPC: G06F15/80 ,  G06F9/38 ,  G06F9/30 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F9/3887 ,  G06F9/30098 ,  G06T1/20 ,  G06T1/60

Abstract: Techniques are disclosed relating to operand routing among SIMD pipelines. In some embodiments, an apparatus includes a set of multiple hardware pipelines configured to execute a single-instruction multiple-data (SIMD) instruction for multiple threads in parallel, wherein the instruction specifies first and second architectural registers. In some embodiments, the pipelines include execution circuitry configured to perform operations using one or more pipeline stages of the pipeline. In some embodiments, the pipelines include routing circuitry configured to select, based on the instruction, a first input operand for the execution circuitry from among: a value from the first architectural register from thread-specific storage for another pipeline and a value from the second architectural register from thread-specific storage for a thread assigned to another pipeline. In some embodiments, the routing circuitry may support a shift and fill instruction that facilitates storage of an arbitrary portion of a graphics frame in one or more registers.

公开(公告)号：US10387119B2

公开(公告)日：2019-08-20

申请号：US16146147

申请日：2018-09-28

Applicant: Apple Inc.

Inventor： Liang-Kai Wang ,  Terence M. Potter ,  Brian K. Reynolds ,  Justin Friesenhahn

IPC: G06F7/505 ,  G06F9/30 ,  G06T9/00

Abstract: Techniques are disclosed relating to performing arithmetic operations to generate values for different related threads. In some embodiments, the threads are graphics threads and the values are operand locations. In some embodiments, an apparatus includes circuitry configured to generate results for multiple threads by performing a plurality of arithmetic operations indicated by an instruction. In some embodiments, the instruction specifies: an input value that is common to the multiple threads and, for at least one of the multiple threads, a type value that indicates whether to generate a result for the thread by performing an arithmetic operation based on a first input that is a result of an arithmetic operation from another thread of the multiple threads or to generate a result for the thread using the input value that is common to the multiple threads. In some embodiments, the circuitry is configured to generate a result for the at least one of the multiple threads by selectively performing the arithmetic operation or using the input value that is common to the multiple threads based on the type value.

公开(公告)号：US10324844B2

公开(公告)日：2019-06-18

申请号：US15389047

申请日：2016-12-22

Applicant: Apple Inc.

Inventor： Anthony P. DeLaurier ,  Owen C. Anderson ,  Michael J. Swift ,  Aaftab A. Munshi ,  Terence M. Potter

IPC: G09G5/36 ,  G06F12/0815 ,  G06F12/0811 ,  G06F12/084 ,  G06T1/60

Abstract: Techniques are disclosed relating to memory consistency in a memory hierarchy with relaxed ordering. In some embodiments, an apparatus includes a first level cache that is shared by a plurality of shader processing elements and a second level cache that is shared by the shader processing elements and at least a texture processing unit. In some embodiments, the apparatus is configured to execute operations specified by graphics instructions that include (1) an attribute of the operation that specifies a type of memory consistency to be imposed for the operation and (2) scope information for the attribute that specifies whether the memory consistency specified by the attribute should be enforced at the first level cache or the second level cache. In some embodiments, the apparatus is configured to determine whether to sequence memory accesses at the first level cache and the second level cache based on the attribute and the scope.

公开(公告)号：US20180067748A1

公开(公告)日：2018-03-08

申请号：US15257386

申请日：2016-09-06

Applicant: Apple Inc.

Inventor： Andrew M. Havlir ,  Brian K. Reynolds ,  Liang Xia ,  Terence M. Potter

IPC: G06F9/38

CPC classification number: G06F9/3867 ,  G06F9/3851 ,  G06F9/3887

Abstract: Techniques are disclosed relating to clause-based execution of program instructions, which may be single-instruction multiple data (SIMD) computer instructions. In some embodiments, an apparatus includes execution circuitry configured to receive clauses of instructions and SIMD groups of input data to be operated on by the clauses. In some embodiments, the apparatus further includes one or more storage elements configured to store state information for clauses processed by the execution circuitry. In some embodiments, the apparatus further includes scheduling circuitry configured to send instructions of a first clause and corresponding input data for execution by the execution circuitry and indicate, prior to sending instruction and input data of a second clause to the execution circuitry for execution, whether the second clause and a first clause are assigned to operate on groups of input data corresponding to the same instruction stream. In some embodiments, the apparatus is configured to determine, based on the indication, whether to maintain as valid, for use by the second clause, stored state information for the first clause.

公开(公告)号：US20170357506A1

公开(公告)日：2017-12-14

申请号：US15180725

申请日：2016-06-13

Applicant: Apple Inc.

Inventor： Liang-Kai Wang ,  Terence M. Potter ,  Andrew M. Havlir

IPC: G06F9/30

CPC classification number: G06F9/30021 ,  G06F9/3001 ,  G06F9/30083

Abstract: Techniques are disclosed relating to comparison circuitry. In some embodiments, compare circuitry is configured to generate comparison results for sets of inputs in both one or more integer formats and one or more floating-point formats. In some embodiments, the compare circuitry includes padding circuitry configured to add one or more bits to each of first and second input values to generate first and second padded values. In some embodiments, the compare circuitry also includes integer subtraction circuitry configured to subtract the first padded value from the second padded value to generate a subtraction result. In some embodiments, the compare circuitry includes output logic configured to generate the comparison result based on the subtraction result. In various embodiments, using at least a portion of the same circuitry (e.g., the subtractor) for both integer and floating-point comparisons may reduce processor area.

公开(公告)号：US20170293470A1

公开(公告)日：2017-10-12

申请号：US15092401

申请日：2016-04-06

Applicant: Apple Inc.

Inventor： Liang-Kai Wang ,  Terence M. Potter ,  Andrew M. Havlir ,  Yu Sun ,  Nicolas X. Pena ,  Xiao-Long Wu ,  Christopher A. Burns

IPC: G06F7/483

CPC classification number: G06F7/483 ,  G06F7/5443

Abstract: Techniques are disclosed relating to floating-point operations with down-conversion. In some embodiments, a floating-point unit is configured to perform fused multiply-addition operations based on first and second different instruction types. In some embodiments, the first instruction type specifies result in the first floating-point format and the second instruction type specifies fused multiply addition of input operands in the first floating-point format to generate a result in a second, lower-precision floating-point format. For example, the first format may be a 32-bit format and the second format may be a 16-bit format. In some embodiments, the floating-point unit includes rounding circuitry, exponent circuitry, and/or increment circuitry configured to generate signals for the second instruction type in the same pipeline stage as for the first instruction type. In some embodiments, disclosed techniques may reduce the number of pipeline stages included in the floating-point circuitry.

公开(公告)号：US09785567B2

公开(公告)日：2017-10-10

申请号：US14851859

申请日：2015-09-11

Applicant: Apple Inc.

Inventor： Andrew M. Havlir ,  Terence M. Potter ,  Liang-Kai Wang

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/0884 ,  G06F12/0846 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F12/0884 ,  G06F9/3012 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3859 ,  G06F12/0848 ,  G06F2212/604

Abstract: Techniques are disclosed relating to per-pipeline control for an operand cache. In some embodiments, an apparatus includes a register file and multiple execution pipelines. In some embodiments, the apparatus also includes an operand cache that includes multiple entries that each include multiple portions that are each configured to store an operand for a corresponding execution pipeline. In some embodiments, the operand cache is configured, during operation of the apparatus, to store data in only a subset of the portions of an entry. In some embodiments, the apparatus is configured to store, for each entry in the operand cache, a per-entry validity value that indicates whether the entry is valid and per-portion state information that indicates whether data for each portion is valid and whether data for each portion is modified relative to data in a corresponding entry in the register file.

公开(公告)号：US09619394B2

公开(公告)日：2017-04-11

申请号：US14805124

申请日：2015-07-21

Applicant: Apple Inc.

Inventor： Andrew M. Havlir ,  Terence M. Potter

IPC: G06F13/00 ,  G06F12/0875 ,  G06F12/0891 ,  G06F9/30 ,  G06F12/0815

CPC classification number: G06F12/0875 ,  G06F9/383 ,  G06F12/0815 ,  G06F12/126 ,  G06F2212/1028 ,  G06F2212/1056 ,  G06F2212/452 ,  G06F2212/6046 ,  Y02D10/13

Abstract: An apparatus includes an operand cache for storing operands from a register file for use by execution circuitry. In some embodiments, eviction priority for the operand cache is based on the status of entries (e.g., whether dirty or clean) and the retention priority of entries. In some embodiments, flushes are handled differently based on their retention priority (e.g., low-priority entries may be pre-emptively flushed). In some embodiments, timing for cache clean operations is specified on a per-instruction basis. Disclosed techniques may spread out write backs in time, facilitate cache clean operations, facilitate thread switching, extend the time operands are available in an operand cache, and/or improve the use of compiler hints, in some embodiments.

公开(公告)号：US20160350113A1

公开(公告)日：2016-12-01

申请号：US15233496

申请日：2016-08-10

Applicant: Apple Inc.

Inventor： James S. Blomgren ,  Terence M. Potter

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30007 ,  G06F9/34 ,  G06F9/384 ,  G06F9/3857

Abstract: Techniques are disclosed relating to specification of instruction operands. In some embodiments, this may involve assigning operands to source inputs. In one embodiment, an instruction includes one or more mapping values, each of which corresponds to a source of the instruction and each of which specifies a location value. In this embodiment, the instruction includes one or more location values that are each usable to identify an operand for the instruction. In this embodiment, a method may include accessing operands using the location values and assigning accessed operands to sources using the mapping values. In one embodiment, the sources may correspond to inputs of an execution block. In one embodiment, a destination mapping value in the instruction may specify a location value that indicates a destination for storing an instruction result.