公开(公告)号：US09645791B2

公开(公告)日：2017-05-09

申请号：US14305651

申请日：2014-06-16

Applicant: Apple Inc.

Inventor： Boris S Alvarez-Heredia ,  Edvin Catovic

IPC: G06F7/544 ,  G06F7/535 ,  G06F7/552 ,  G06F7/499

CPC classification number: G06F7/5443 ,  G06F7/49936 ,  G06F7/49947 ,  G06F7/535 ,  G06F7/5525 ,  G06F2207/5355

Abstract: Embodiments of a multiplier unit that may be used for division and square root operations are disclosed. The embodiments may provide a reduced and fixed latency for denormalization and rounding used in the division and square root operations. A storage circuit may be configured to receive first and second source operands. A multiplier circuit may be configured to perform a plurality of multiplication operations dependent upon the first and second source operands. Each result after an initial result of the multiplier may also depend on at least one previous result. Circuitry may be configured to perform a shift operation and a rounding operation on a given result of the plurality of results. An error of the given result may be less than a predetermined threshold value.

公开(公告)号：US20150363169A1

公开(公告)日：2015-12-17

申请号：US14305651

申请日：2014-06-16

Applicant: Apple Inc.

Inventor： Boris S Alvarez-Heredia ,  Edvin Catovic

IPC: G06F7/52 ,  G06F5/01 ,  G06F7/544

CPC classification number: G06F7/5443 ,  G06F7/49936 ,  G06F7/49947 ,  G06F7/535 ,  G06F7/5525 ,  G06F2207/5355

Abstract: Embodiments of a multiplier unit that may be used for division and square root operations are disclosed. The embodiments may provide a reduced and fixed latency for denormalization and rounding used in the division and square root operations. A storage circuit may be configured to receive first and second source operands. A multiplier circuit may be configured to perform a plurality of multiplication operations dependent upon the first and second source operands. Each result after an initial result of the multiplier may also depend on at least one previous result. Circuitry may be configured to perform a shift operation and a rounding operation on a given result of the plurality of results. An error of the given result may be less than a predetermined threshold value.

Abstract translation: 公开了可用于划分和平方根操作的乘法器单元的实施例。 这些实施例可以为分割和平方根操作中使用的非归一化和舍入提供减小和固定的等待时间。 存储电路可以被配置为接收第一和第二源操作数。 乘法器电路可以被配置为执行依赖于第一和第二源操作数的多个乘法运算。 乘法器的初始结果之后的每个结果也可以取决于至少一个先前的结果。 电路可以被配置为对多个结果的给定结果执行移位操作和舍入操作。 给定结果的误差可能小于预定阈值。