公开(公告)号：US09645791B2

公开(公告)日：2017-05-09

申请号：US14305651

申请日：2014-06-16

Applicant: Apple Inc.

Inventor： Boris S Alvarez-Heredia ,  Edvin Catovic

IPC: G06F7/544 ,  G06F7/535 ,  G06F7/552 ,  G06F7/499

CPC classification number: G06F7/5443 ,  G06F7/49936 ,  G06F7/49947 ,  G06F7/535 ,  G06F7/5525 ,  G06F2207/5355

Abstract: Embodiments of a multiplier unit that may be used for division and square root operations are disclosed. The embodiments may provide a reduced and fixed latency for denormalization and rounding used in the division and square root operations. A storage circuit may be configured to receive first and second source operands. A multiplier circuit may be configured to perform a plurality of multiplication operations dependent upon the first and second source operands. Each result after an initial result of the multiplier may also depend on at least one previous result. Circuitry may be configured to perform a shift operation and a rounding operation on a given result of the plurality of results. An error of the given result may be less than a predetermined threshold value.

公开(公告)号：US20160241240A1

公开(公告)日：2016-08-18

申请号：US14622111

申请日：2015-02-13

Applicant: Apple Inc.

Inventor： Shingo Suzuki ,  Harsha Krishnamurthy ,  Edvin Catovic ,  Rajat Goel ,  Manoj Gopalan

IPC: H03K19/003 ,  H03K19/00

CPC classification number: H03K19/00361 ,  H03K19/0013 ,  H03K19/0016

Abstract: In an embodiment, an integrated circuit may include one or more power gated blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power gated block and a block enable clock. The power gated block may generate local block enables to various power switch segments in the power gated block. In particular, the power gated block may include a set of series-connected flops that receive the block enable from the power manager circuit. The power gated block may include a set of multiplexors (muxes) that provide the local block enables for each power switch segment. One input of the muxes is coupled to the block enable, and the other input is coupled to another enable propagated through one of the other power switch segments. Accordingly, the muxes may be controlled to select the propagated enables or the input block enable.

Abstract translation: 在一个实施例中，集成电路可以包括一个或多个电源门控块和功率管理器电路。 功率管理器电路可以被配置为为每个电源门控块和块使能时钟生成块使能。 电源门控块可以在电源门控块中产生各种电源开关段的本地块使能。 特别地，电源门控块可以包括从电源管理器电路接收块使能的一组串联的触发器。 功率门控块可以包括为每个功率开关段提供本地块使能的一组多路复用器（多路复用器）。 多路复用器的一个输入耦合到块使能，另一个输入耦合到通过其它功率开关段之一传播的另一个功能。 因此，可以控制多路复用器来选择传播的使能或输入块使能。

公开(公告)号：US10037073B1

公开(公告)日：2018-07-31

申请号：US15273925

申请日：2016-09-23

Applicant: Apple Inc.

Inventor： Edvin Catovic ,  Rajat Goel ,  Richard F. Russo ,  Matthew R. Johnson ,  Shingo Suzuki ,  Pradeep Kanapathipillai ,  Raghava Rao V. Denduluri ,  Pankaj Lnu

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3243

Abstract: A processor includes an instruction issue circuit, and high-utilization and low-utilization execution unit circuits coupled to execute instructions received from the instruction issue unit. On average, utilization of the low-utilization execution unit circuit is lower than utilization of the high-utilization execution unit circuit. The processor also includes a retention circuit coupled to a different power domain than the low-utilization execution unit circuit, and a power management circuit. The power management circuit may be configured to detect that inactivity of the low-utilization execution unit circuit satisfies a threshold inactivity level; upon detecting that the threshold inactivity level is satisfied, cause architecturally-visible state of the low-utilization execution unit circuit to be copied to the retention circuit; and subsequent to copying of the architecturally-visible state to the retention circuit, cause the low-utilization execution unit circuit to enter a power-off state, where the retention circuit retains stored data during the power-off state.

公开(公告)号：US20150363169A1

公开(公告)日：2015-12-17

申请号：US14305651

申请日：2014-06-16

Applicant: Apple Inc.

Inventor： Boris S Alvarez-Heredia ,  Edvin Catovic

IPC: G06F7/52 ,  G06F5/01 ,  G06F7/544

CPC classification number: G06F7/5443 ,  G06F7/49936 ,  G06F7/49947 ,  G06F7/535 ,  G06F7/5525 ,  G06F2207/5355

Abstract: Embodiments of a multiplier unit that may be used for division and square root operations are disclosed. The embodiments may provide a reduced and fixed latency for denormalization and rounding used in the division and square root operations. A storage circuit may be configured to receive first and second source operands. A multiplier circuit may be configured to perform a plurality of multiplication operations dependent upon the first and second source operands. Each result after an initial result of the multiplier may also depend on at least one previous result. Circuitry may be configured to perform a shift operation and a rounding operation on a given result of the plurality of results. An error of the given result may be less than a predetermined threshold value.

Abstract translation: 公开了可用于划分和平方根操作的乘法器单元的实施例。 这些实施例可以为分割和平方根操作中使用的非归一化和舍入提供减小和固定的等待时间。 存储电路可以被配置为接收第一和第二源操作数。 乘法器电路可以被配置为执行依赖于第一和第二源操作数的多个乘法运算。 乘法器的初始结果之后的每个结果也可以取决于至少一个先前的结果。 电路可以被配置为对多个结果的给定结果执行移位操作和舍入操作。 给定结果的误差可能小于预定阈值。

公开(公告)号：US09564898B2

公开(公告)日：2017-02-07

申请号：US14622111

申请日：2015-02-13

Applicant: Apple Inc.

Inventor： Shingo Suzuki ,  Harsha Krishnamurthy ,  Edvin Catovic ,  Rajat Goel ,  Manoj Gopalan

IPC: H03K19/003 ,  H03K19/00

CPC classification number: H03K19/00361 ,  H03K19/0013 ,  H03K19/0016

Abstract: In an embodiment, an integrated circuit may include one or more power gated blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power gated block and a block enable clock. The power gated block may generate local block enables to various power switch segments in the power gated block. In particular, the power gated block may include a set of series-connected flops that receive the block enable from the power manager circuit. The power gated block may include a set of multiplexors (muxes) that provide the local block enables for each power switch segment. One input of the muxes is coupled to the block enable, and the other input is coupled to another enable propagated through one of the other power switch segments. Accordingly, the muxes may be controlled to select the propagated enables or the input block enable.

Abstract translation: 在一个实施例中，集成电路可以包括一个或多个电源门控块和功率管理器电路。 功率管理器电路可以被配置为为每个电源门控块和块使能时钟生成块使能。 电源门控块可以在电源门控块中产生各种电源开关段的本地块使能。 特别地，电源门控块可以包括从电源管理器电路接收块使能的一组串联的触发器。 功率门控块可以包括为每个功率开关段提供本地块使能的一组多路复用器（多路复用器）。 多路复用器的一个输入耦合到块使能，另一个输入耦合到通过其它功率开关段之一传播的另一个功能。 因此，可以控制多路复用器来选择传播的使能或输入块使能。