公开(公告)号：US10437639B2

公开(公告)日：2019-10-08

申请号：US15786466

申请日：2017-10-17

Applicant: Apple Inc.

Inventor： Russell A. Blaine ,  Daniel A. Chimene ,  Shantonu Sen ,  John Dorsey ,  Bryan Hinch ,  Cyril De La Cropte De Chanterac ,  Oliver Cozette

IPC: G06F9/48 ,  G06F9/52

Abstract: In one embodiment, an application programming interface (API) is defined that enables a thread scheduler to communicate thread information to the CPU performance controller when dispatching a thread to a processor or processor core. When dispatching a thread, the scheduler may communicate thread information including thread state information, a general “importance” of the thread as defined by a priority level and/or quality of service (QoS) classification, a measurement of the scheduler dispatch latency for the thread, or architectural information regarding the instructions within the thread, such as whether the thread is contains 64-bit or 32-bit instructions. The performance controller can use the information provided by the scheduler to make performance control decisions for the processor cores within the system.

公开(公告)号：US20180088985A1

公开(公告)日：2018-03-29

申请号：US15786466

申请日：2017-10-17

Applicant: Apple Inc.

Inventor： Russell A. Blaine ,  Daniel A. Chimene ,  Shantonu Sen ,  John Dorsey ,  Bryan Hinch ,  Cyril De La Cropte De Chanterac ,  Oliver Cozette

IPC: G06F9/48 ,  G06F9/52 ,  G06F9/50

CPC classification number: G06F9/4881 ,  G06F9/4893 ,  G06F9/52 ,  Y02D10/24

Abstract: In one embodiment, an application programming interface (API) is defined that enables a thread scheduler to communicate thread information to the CPU performance controller when dispatching a thread to a processor or processor core. When dispatching a thread, the scheduler may communicate thread information including thread state information, a general “importance” of the thread as defined by a priority level and/or quality of service (QoS) classification, a measurement of the scheduler dispatch latency for the thread, or architectural information regarding the instructions within the thread, such as whether the thread is contains 64-bit or 32-bit instructions. The performance controller can use the information provided by the scheduler to make performance control decisions for the processor cores within the system.

公开(公告)号：US09830187B1

公开(公告)日：2017-11-28

申请号：US14732266

申请日：2015-06-05

Applicant: Apple Inc.

Inventor： Russell A. Blaine ,  Daniel A. Chimene ,  Shantonu Sen ,  John Dorsey ,  Bryan Hinch ,  Cyril De La Cropte De Chanterac ,  Olivier Cozelle

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/50 ,  G06F9/52

CPC classification number: G06F9/4881 ,  G06F9/4893 ,  G06F9/52

Abstract: In one embodiment, an application programming interface (API) is defined that enables a thread scheduler to communicate thread information to the CPU performance controller when dispatching a thread to a processor or processor core. When dispatching a thread, the scheduler may communicate thread information including thread state information, a general “importance” of the thread as defined by a priority level and/or quality of service (QoS) classification, a measurement of the scheduler dispatch latency for the thread, or architectural information regarding the instructions within the thread, such as whether the thread is contains 64-bit or 32-bit instructions. The performance controller can use the information provided by the scheduler to make performance control decisions for the processor cores within the system.