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公开(公告)号:US20240372555A1
公开(公告)日:2024-11-07
申请号:US18312393
申请日:2023-05-04
Applicant: Apple Inc.
Inventor: Thomas Mayer , Christian Wicpalek , Juergen Koechl , Jongmin Park
Abstract: An electronic device may include wireless circuitry with first and second mixers on a signal path for converting a signal using first and second clock signals via high side injection (HSI) or low side injection (LSI). A first phase-locked loop (PLL) may generate the first clock signal and a second PLL may generate the second clock signal. A switch may couple the first PLL to a reference oscillator when LSI is used and may couple the first PLL to a third PLL when HSI is used. The third PLL may generate a second reference signal based on a first reference signal from the reference oscillator. The second PLL may generate the second clock signal based on the output of the third PLL. This may serve to may minimize phase noise even as the mixers switch between HSI and LSI.
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公开(公告)号:US20210392585A1
公开(公告)日:2021-12-16
申请号:US17460941
申请日:2021-08-30
Applicant: Apple Inc.
Inventor: Christian Drewes , Giuseppe Patane , Thomas Mayer , Christian Wicpalek , Ram Kanumalli , Burkhard Neurauter
Abstract: A receiver includes a tunable receiving chain, configured to receive a subframe header when tuned to a first receiving bandwidth; a decoder, configured to decode an allocation information from the subframe header, the allocation information indicating an allocation of a plurality of resource blocks in the subframe; and a controller, configured to derive a second receiving bandwidth from the allocation information and to tune the receiving chain to the second receiving bandwidth.
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公开(公告)号:US11902899B2
公开(公告)日:2024-02-13
申请号:US17460941
申请日:2021-08-30
Applicant: Apple Inc.
Inventor: Christian Drewes , Giuseppe Patane , Thomas Mayer , Christian Wicpalek , Ram Kanumalli , Burkhard Neurauter
IPC: H04W52/02 , H04B1/00 , H04W72/0446 , H04W72/23
CPC classification number: H04W52/0235 , H04B1/0082 , H04W72/0446 , H04W72/23
Abstract: A receiver includes a tunable receiving chain, configured to receive a subframe header when tuned to a first receiving bandwidth; a decoder, configured to decode an allocation information from the subframe header, the allocation information indicating an allocation of a plurality of resource blocks in the subframe; and a controller, configured to derive a second receiving bandwidth from the allocation information and to tune the receiving chain to the second receiving bandwidth.
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公开(公告)号:US11190194B2
公开(公告)日:2021-11-30
申请号:US16977582
申请日:2018-03-31
Applicant: Apple Inc.
Inventor: Christian Wicpalek , Andreas Roithmeier , Andreas Leistner , Thomas Gustedt , Herwig Dietl-Steinmaurer , Tobias Buckel
Abstract: A digital phase-locked loop has a digitally controlled oscillator with a first coarse tuning field for coarse tuning of the oscillator frequency, a second coarse tuning field for tuning of the oscillator frequency at finer intervals than the first coarse tuning field, and a fine tuning field for tuning the oscillator to an output frequency at finer intervals than the second coarse tuning field. The second coarse tuning field provides open loop tuning and is linear and connected parallel to the first coarse tuning field. The second coarse tuning field provides wide field temperature compensation and frequency error determination at start up based on an interpolated frequency value obtained prior to start up. Faster settling is provided with less complex algorithms.
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公开(公告)号:US11109317B2
公开(公告)日:2021-08-31
申请号:US15760859
申请日:2016-08-22
Applicant: Apple Inc.
Inventor: Christian Drewes , Giuseppe Patane , Thomas Mayer , Christian Wicpalek , Ram Kanumalli , Burkhard Neurauter
Abstract: A receiver includes a tunable receiving chain, configured to receive a subframe header when tuned to a first receiving bandwidth; a decoder, configured to decode an allocation information from the subframe header, the allocation information indicating an allocation of a plurality of resource blocks in the subframe; and a controller, configured to derive a second receiving bandwidth from the allocation information and to tune the receiving chain to the second receiving bandwidth.
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公开(公告)号:US20210013891A1
公开(公告)日:2021-01-14
申请号:US16977582
申请日:2018-03-31
Applicant: Apple Inc.
Inventor: Christian Wicpalek , Andreas Roithmeier , Andreas Leistner , Thomas Gustedt , Herwig Dietl-Steinmaurer , Tobias Buckel
Abstract: A digital phase-locked loop has a digitally controlled oscillator with a first coarse tuning field for coarse tuning of the oscillator frequency, a second coarse tuning field for tuning of the oscillator frequency at finer intervals than the first coarse tuning field, and a fine tuning field for tuning the oscillator to an output frequency at finer intervals than the second coarse tuning field. The second coarse tuning field provides open loop tuning and is linear and connected parallel to the first coarse tuning field. The second coarse tuning field provides wide field temperature compensation and frequency error determination at start up based on an interpolated frequency value obtained prior to start up. Faster settling is provided with less complex algorithms.
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