公开(公告)号：US20250094567A1

公开(公告)日：2025-03-20

申请号：US18510540

申请日：2023-11-15

Applicant: Apple Inc.

Inventor： John D Pape ,  Deepankar Duggal ,  Christopher M Tsay ,  Andrew H Lin ,  Corey C Stappenbeck

IPC: G06F21/54 ,  G06F21/55

Abstract: In an embodiment, a processor includes hardware circuitry which may be used to authenticate instruction operands. The processor may execute instructions that perform operand authentication both speculatively and non-speculatively. During speculative execution of such instructions, the processor may execute authentication such that no differences in observable state of the processor, relative to authentication result, are detectable via a side channel. During speculative execution, a result of authentication may be deferred until speculative execution of the instruction, and additional instructions, may be completed. Upon resolution of a condition that indicates acceptance of the speculative execution, a speculative execution result may cause a processor exception and stalling of execution at the instruction to be performed.