公开(公告)号：US11630771B2

公开(公告)日：2023-04-18

申请号：US17373814

申请日：2021-07-13

Applicant: APPLE INC.

Inventor： John D Pape ,  Mahesh K Reddy ,  Prasanna Utchani Varadharajan ,  Pruthivi Vuyyuru

IPC: G06F12/0802

Abstract: An apparatus includes multiple processors including respective cache memories, the cache memories configured to cache cache-entries for use by the processors. At least a processor among the processors includes cache management logic that is configured to (i) receive, from one or more of the other processors, cache-invalidation commands that request invalidation of specified cache-entries in the cache memory of the processor (ii) mark the specified cache-entries as intended for invalidation but defer actual invalidation of the specified cache-entries, and (iii) upon detecting a synchronization event associated with the cache-invalidation commands, invalidate the cache-entries that were marked as intended for invalidation.

公开(公告)号：US20250094567A1

公开(公告)日：2025-03-20

申请号：US18510540

申请日：2023-11-15

Applicant: Apple Inc.

Inventor： John D Pape ,  Deepankar Duggal ,  Christopher M Tsay ,  Andrew H Lin ,  Corey C Stappenbeck

IPC: G06F21/54 ,  G06F21/55

Abstract: In an embodiment, a processor includes hardware circuitry which may be used to authenticate instruction operands. The processor may execute instructions that perform operand authentication both speculatively and non-speculatively. During speculative execution of such instructions, the processor may execute authentication such that no differences in observable state of the processor, relative to authentication result, are detectable via a side channel. During speculative execution, a result of authentication may be deferred until speculative execution of the instruction, and additional instructions, may be completed. Upon resolution of a condition that indicates acceptance of the speculative execution, a speculative execution result may cause a processor exception and stalling of execution at the instruction to be performed.

公开(公告)号：US12229561B1

公开(公告)日：2025-02-18

申请号：US17933037

申请日：2022-09-16

Applicant: Apple Inc.

Inventor： Madhu Sudan Hari ,  Mridul Agarwal ,  Kulin N Kothari ,  John D Pape ,  Niket K Choudhary

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/52 ,  G06F12/1027

Abstract: A system may include multiple processors. One of the processors may receive an indication of a data synchronization barrier (DSB) instruction in another processor that follows a translation look-ahead buffer invalidate (TLBI) instruction to invalidate an entry of a translation look-ahead buffer. The processor may determine whether instructions are pending in the processor for which the virtual addresses used for memory accesses have been translated to physical addresses before receiving the DSB indication. If there are such pending instructions, the processor may provide, after these instructions retire, an indication to the other processor as a response to the DSB indication.