Method for reducing lock time in a closed loop clock signal generator

    公开(公告)号:US09838025B1

    公开(公告)日:2017-12-05

    申请号:US15233124

    申请日:2016-08-10

    Applicant: Apple Inc.

    CPC classification number: H03L7/0891 H03L7/1072 H03L7/1075 H03L7/113 H03L7/18

    Abstract: An apparatus includes circuitry and an oscillator circuit that may be configured to generate a clock signal dependent upon a control signal. The circuitry may be configured to perform a frequency measurement of the clock signal. In response to a determination that the frequency of the clock signal is greater than a first threshold, the circuitry may also be configured to perform a phase comparison between a divided clock signal and a reference clock signal, and to adjust a value of the control signal such that the adjusted value depends upon a result of the comparison. In response to a determination that the frequency of the clock signal is less than the first threshold, the circuitry may be configured to adjust the value of the control signal such that the adjusted value depends upon a result of the measurement.

Patent Agency Ranking