公开(公告)号：US20250103292A1

公开(公告)日：2025-03-27

申请号：US18426020

申请日：2024-01-29

Applicant: Apple Inc.

Inventor： David K. Li ,  Christopher A. Burns ,  Daniel E. Barnard ,  Evan R. Lissoos

IPC: G06F7/544 ,  G06F7/501 ,  G06F17/16

Abstract: Techniques are disclosed relating to integrated circuits that support matrix operations. In various embodiments, an integrated circuit comprises a dot product accumulate circuit that includes a dot product circuit configured to determine a dot product of a first vector and a second vector, and an adder circuit coupled to an output of the dot product circuit and configured to add a result of the dot product and an accumulation value. The integrated circuit further includes an accumulator cache coupled to an input of the adder circuit and an output of the adder circuit. The accumulator cache is configured to provide the accumulation value to the adder circuit and store a result of the add as a subsequent accumulation value for a subsequent dot product accumulate operation.