中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

10 records (took 0.017 seconds)

    Systems and methods for arbitrating traffic in a bus
    2.
    发明授权
    Systems and methods for arbitrating traffic in a bus 有权

    公开(公告)号：US11748284B2

    公开(公告)日：2023-09-05

    申请号：US17375565

    申请日：2021-07-14

    Applicant: Apple Inc.

    Inventor： Nachiappan Chidambaram Nachiappan ,  Jaideep Dastidar ,  Yiu Chun Tse ,  Ripudaman Singh ,  Shawn Munetoshi Fukami ,  Benjamin K. Dodge ,  Vinodh R. Cuppu

    IPC: G06F13/366 ,  G06F13/40

    CPC classification number: G06F13/366 ,  G06F13/4031

    Abstract: A system and method for efficiently arbitrating traffic on a bus. A computing system includes a fabric for routing traffic among one or more agents and one or more endpoints. The fabric includes multiple arbiters in an arbitration hierarchy. Arbiters store traffic in buffers with each buffer associated with a particular traffic type and a source of the traffic. Arbiters maintain a respective urgency counter for keeping track of a period of time traffic of a particular type is blocked by upstream arbiters. When the block is removed, the traffic of the particular type has priority for selection based on the urgency counter. When arbiters receive feedback from downstream arbiters or sources, the arbiters adjust selection priority accordingly. For example, changes in bandwidth requirement, low latency tolerance and active status cause adjustments in selection priority of stored requests.

    Systems and Methods for Arbitrating Traffic in a Bus
    3.
    发明申请
    Systems and Methods for Arbitrating Traffic in a Bus 有权

    公开(公告)号：US20210342282A1

    公开(公告)日：2021-11-04

    申请号：US17375565

    申请日：2021-07-14

    Applicant: Apple Inc.

    Inventor： Nachiappan Chidambaram Nachiappan ,  Jaideep Dastidar ,  Yiu Chun Tse ,  Ripudaman Singh ,  Shawn Munetoshi Fukami ,  Benjamin K. Dodge ,  Vinodh R. Cuppu

    IPC: G06F13/366 ,  G06F13/40

    Abstract: A system and method for efficiently arbitrating traffic on a bus. A computing system includes a fabric for routing traffic among one or more agents and one or more endpoints. The fabric includes multiple arbiters in an arbitration hierarchy. Arbiters store traffic in buffers with each buffer associated with a particular traffic type and a source of the traffic. Arbiters maintain a respective urgency counter for keeping track of a period of time traffic of a particular type is blocked by upstream arbiters. When the block is removed, the traffic of the particular type has priority for selection based on the urgency counter. When arbiters receive feedback from downstream arbiters or sources, the arbiters adjust selection priority accordingly. For example, changes in bandwidth requirement, low latency tolerance and active status cause adjustments in selection priority of stored requests.

    SYSTEMS AND METHODS FOR ARBITRATING TRAFFIC IN A BUS
    4.
    发明申请
    SYSTEMS AND METHODS FOR ARBITRATING TRAFFIC IN A BUS 审中-公开

    公开(公告)号：US20200057737A1

    公开(公告)日：2020-02-20

    申请号：US16105252

    申请日：2018-08-20

    Applicant: Apple Inc.

    Inventor： Nachiappan Chidambaram Nachiappan ,  Jaideep Dastidar ,  Yiu Chun Tse ,  Ripudaman Singh ,  Shawn Munetoshi Fukami ,  Benjamin K. Dodge ,  Vinodh R. Cuppu

    IPC: G06F13/366 ,  G06F13/40

    Abstract: A system and method for efficiently arbitrating traffic on a bus. A computing system includes a fabric for routing traffic among one or more agents and one or more endpoints. The fabric includes multiple arbiters in an arbitration hierarchy. Arbiters store traffic in buffers with each buffer associated with a particular traffic type and a source of the traffic. Arbiters maintain a respective urgency counter for keeping track of a period of time traffic of a particular type is blocked by upstream arbiters. When the block is removed, the traffic of the particular type has priority for selection based on the urgency counter. When arbiters receive feedback from downstream arbiters or sources, the arbiters adjust selection priority accordingly. For example, changes in bandwidth requirement, low latency tolerance and active status cause adjustments in selection priority of stored requests.

    Systems and methods for arbitrating traffic in a bus
    6.
    发明授权
    Systems and methods for arbitrating traffic in a bus 有权

    公开(公告)号：US11093425B2

    公开(公告)日：2021-08-17

    申请号：US16105252

    申请日：2018-08-20

    Applicant: Apple Inc.

    Inventor： Nachiappan Chidambaram Nachiappan ,  Jaideep Dastidar ,  Yiu Chun Tse ,  Ripudaman Singh ,  Shawn Munetoshi Fukami ,  Benjamin K. Dodge ,  Vinodh R. Cuppu

    IPC: G06F13/40 ,  G06F13/366

    Abstract: A system and method for efficiently arbitrating traffic on a bus. A computing system includes a fabric for routing traffic among one or more agents and one or more endpoints. The fabric includes multiple arbiters in an arbitration hierarchy. Arbiters store traffic in buffers with each buffer associated with a particular traffic type and a source of the traffic. Arbiters maintain a respective urgency counter for keeping track of a period of time traffic of a particular type is blocked by upstream arbiters. When the block is removed, the traffic of the particular type has priority for selection based on the urgency counter. When arbiters receive feedback from downstream arbiters or sources, the arbiters adjust selection priority accordingly. For example, changes in bandwidth requirement, low latency tolerance and active status cause adjustments in selection priority of stored requests.

    SYSTEMS AND METHODS FOR OPTIMIZING SCHEDULING DIFFERENT TYPES OF MEMORY REQUESTS WITH VARYING DATA SIZES
    7.
    发明申请
    SYSTEMS AND METHODS FOR OPTIMIZING SCHEDULING DIFFERENT TYPES OF MEMORY REQUESTS WITH VARYING DATA SIZES 审中-公开

    公开(公告)号：US20200042469A1

    公开(公告)日：2020-02-06

    申请号：US16056376

    申请日：2018-08-06

    Applicant: Apple Inc.

    Inventor： Shawn Munetoshi Fukami ,  Jaideep Dastidar ,  Yiu Chun Tse

    IPC: G06F13/16 ,  G06F9/48

    Abstract: A system and method for efficiently scheduling requests. In various embodiments, a processor sends commands such as read requests and write requests to an arbiter. The arbiter reduces latencies between commands being sent to a communication fabric and corresponding data being sent to the fabric. When the arbiter selects a given request, the arbiter identifies a first subset of stored requests affected by the given request being selected. The arbiter adjusts one or more attributes of the first subset of requests based on the selection of the given request. In one example, the arbiter replaces a weight attribute with a value, such as a zero value, indicating the first subset of requests should not be selected. Therefore, during the next selection by the arbiter, only the requests in a second subset different from the first subset are candidates for selection.

    Systems and methods for controlling data on a bus using latency
    8.
    发明授权
    Systems and methods for controlling data on a bus using latency 有权

    公开(公告)号：US10423558B1

    公开(公告)日：2019-09-24

    申请号：US16058433

    申请日：2018-08-08

    Applicant: Apple Inc.

    Inventor： Shawn Munetoshi Fukami ,  Yiu Chun Tse ,  David L. Trawick ,  Hengsheng Geng ,  Jaideep Dastidar ,  Vinodh R. Cuppu ,  Deniz Balkan

    IPC: G06F3/06 ,  G06F13/40 ,  G06F13/16 ,  G06F13/362 ,  G06F9/54 ,  G06F13/18

    Abstract: A system and method for efficiently routing data in a communication fabric. A computing system includes a fabric for routing data among one or more agents and a memory controller for system memory. The fabric includes multiple hierarchical clusters with a split topology where the data links are physically separated from the control links. A given cluster receives a write command and associated write data, and stores them in respective buffers. The given cluster marks the write command as a candidate to be issued to the memory controller when it is determined the write data will arrive ahead of the write command at the memory controller after being issued. The given cluster prevents the write command from becoming a candidate to be issued when it is determined the write data may not arrive ahead of the write command at the memory controller.

    Systems and methods for scheduling different types of memory requests with varying data sizes
    9.
    发明授权
    Systems and methods for scheduling different types of memory requests with varying data sizes 有权

    公开(公告)号：US10649922B2

    公开(公告)日：2020-05-12

    申请号：US16056376

    申请日：2018-08-06

    Applicant: Apple Inc.

    Inventor： Shawn Munetoshi Fukami ,  Jaideep Dastidar ,  Yiu Chun Tse

    IPC: G06F13/14 ,  G06F13/16 ,  G06F9/48

    Abstract: A system and method for efficiently scheduling requests. In various embodiments, a processor sends commands such as read requests and write requests to an arbiter. The arbiter reduces latencies between commands being sent to a communication fabric and corresponding data being sent to the fabric. When the arbiter selects a given request, the arbiter identifies a first subset of stored requests affected by the given request being selected. The arbiter adjusts one or more attributes of the first subset of requests based on the selection of the given request. In one example, the arbiter replaces a weight attribute with a value, such as a zero value, indicating the first subset of requests should not be selected. Therefore, during the next selection by the arbiter, only the requests in a second subset different from the first subset are candidates for selection.

Patent Agency Ranking