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    SYSTEMS, METHODS, AND DEVICES FOR APPLICATION DATA PREBOOKING
    1.
    发明公开
    SYSTEMS, METHODS, AND DEVICES FOR APPLICATION DATA PREBOOKING 审中-公开

    公开(公告)号：US20240188073A1

    公开(公告)日：2024-06-06

    申请号：US18524050

    申请日：2023-11-30

    Applicant: Apple Inc.

    Inventor： Neha Goel ,  Ralph Hasholzner ,  Lakshmi Iyer ,  Mikhail Wilhelm ,  Murali Narasimha ,  Arjun Bharadwaj

    IPC: H04W72/1268 ,  H04W28/02

    CPC classification number: H04W72/1268 ,  H04W28/0278 ,  H04W88/02

    Abstract: An application may provide prebooking information for multiple packet streams to a baseband processor. The prebooking information may include some or all of a first packet stream and information describing one or more additional packet streams. The baseband processor may generate a buffer status report (BSR) corresponding to multiple packet streams to the extent that the data for the packet streams are to arrive at the baseband processor prior to the a preconfigured duration (e.g., the baseband processor receiving a dynamic grant (DG) from the base station). In this sense, application data may be prebooked, by the baseband processor and/or base station, before actually arriving at the baseband processor. These and many other examples and techniques described herein, including the use of dummy packets for a DG, managing DGs based on dummy packets, and more.

    PROCESSOR AND USER EQUIPMENT FOR REDUCING POWER CONSUMPTION DURING DRX
    2.
    发明公开
    PROCESSOR AND USER EQUIPMENT FOR REDUCING POWER CONSUMPTION DURING DRX 审中-公开

    公开(公告)号：US20240008136A1

    公开(公告)日：2024-01-04

    申请号：US17853823

    申请日：2022-06-29

    Applicant: Apple Inc.

    Inventor： Neha Goel ,  Murali Narasimha ,  Sreevalsan Vallath

    IPC: H04W76/28 ,  H04W72/14 ,  H04W72/12

    CPC classification number: H04W76/28 ,  H04W72/1268 ,  H04W72/14

    Abstract: A processor determines that a UE operates in a DRX cycle including a DRX-on duration followed by a DRX-sleep duration. The processor configures a plurality of periodic uplink CG occasions within the DRX cycle. Each uplink CG occasion supports uplink transmission of a predefined size. The processor reads a data buffer to determine a size of accumulated data. At a given uplink CG occasion, the processor compares the size of accumulated data with an upper threshold data size and a lower threshold data size. Responsive to a first comparison result, the processor transmits the accumulated data over one or more uplink CG occasions starting from the given uplink CG occasion. Responsive to a second comparison result, the processor transmits a BSR at the given uplink CG occasion. Responsive to a third comparison result, the processor transmits neither the accumulated data nor the BSR at the given uplink CG occasion.

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