公开(公告)号：US09454482B2

公开(公告)日：2016-09-27

申请号：US13928636

申请日：2013-06-27

Applicant: Apple Inc.

Inventor： Harshavardhan Kaushikkar ,  Muditha Kanchana ,  Odutola O. Ewedemi

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0815

Abstract: An apparatus for processing cache requests in a computing system is disclosed. The apparatus may include a single-port memory, a dual-port memory, and a control circuit. The single-port memory may be store tag information associated with a cache memory, and the dual-port memory may be configured to store state information associated with the cache memory. The control circuit may be configured to receive a request which includes a tag address, access the tag and state information stored in the single-port memory and the dual-port memory, respectively, dependent upon the received tag address. A determination of if the data associated with the received tag address is contained in the cache memory may be made the control circuit, and the control circuit may update and store state information in the dual-port memory responsive to the determination.

Abstract translation: 公开了一种用于处理计算系统中的缓存请求的装置。 该装置可以包括单端口存储器，双端口存储器和控制电路。 单端口存储器可以是与高速缓冲存储器相关联的存储标签信息，并且双端口存储器可以被配置为存储与高速缓冲存储器相关联的状态信息。 控制电路可以被配置为根据接收的标签地址分别接收包括标签地址，访问标签和分别存储在单端口存储器中的状态信息和双端口存储器的请求。 可以确定与接收的标签地址相关联的数据是否包含在高速缓存存储器中，并且控制电路可以响应于该确定来更新和存储双端口存储器中的状态信息。

公开(公告)号：US20150067246A1

公开(公告)日：2015-03-05

申请号：US14013471

申请日：2013-08-29

Applicant: Apple Inc

Inventor： Muditha Kanchana ,  Odutola O. Ewedemi

IPC: G06F12/08 ,  G11C11/406

CPC classification number: G06F12/0831 ,  G06F12/0822

Abstract: An apparatus for processing cache requests in a computing system is disclosed. The apparatus may include a plurality of state memories, a plurality tag memories, and a control circuit. Each of the state memories may be configured to store coherency state information for a cache memory of a respective plurality of coherent agents. Each of the tag memories may be configured to store duplicate tag information a cache memory of the respective plurality of coherent agents. The control circuit may be configured to receive a tag address, access tag information in each of the tag memories in parallel dependent upon the received tag address, determine, for each cache memory, new coherency state information for a cache entry corresponding to the received tag address, and store the new coherency state information for each of the cache memories into a respective one of the plurality of state memories.

Abstract translation: 公开了一种用于处理计算系统中的缓存请求的装置。 该装置可以包括多个状态存储器，多个标签存储器和控制电路。 每个状态存储器可以被配置为存储用于相应多个相干代理的高速缓冲存储器的一致性状态信息。 每个标签存储器可以被配置为将重复的标签信息存储在相应的多个相干代理的高速缓冲存储器中。 控制电路可以被配置为接收标签地址，取决于接收到的标签地址并行地访问每个标签存储器中的标签信息，为每个高速缓冲存储器确定与接收到的标签相对应的高速缓存条目的新的一致性状态信息 地址，并将每个高速缓冲存储器的新的一致性状态信息存储到多个状态存储器的相应一个状态存储器中。

公开(公告)号：US20150006803A1

公开(公告)日：2015-01-01

申请号：US13928636

申请日：2013-06-27

Applicant: Apple Inc.

Inventor： Harshavardhan Kaushikkar ,  Muditha Kanchana ,  Odutola O. Ewedemi

IPC: G06F12/08

CPC classification number: G06F12/0815

Abstract: An apparatus for processing cache requests in a computing system is disclosed. The apparatus may include a single-port memory, a dual-port memory, and a control circuit. The single-port memory may be store tag information associated with a cache memory, and the dual-port memory may be configured to store state information associated with the cache memory. The control circuit may be configured to receive a request which includes a tag address, access the tag and state information stored in the single-port memory and the dual-port memory, respectively, dependent upon the received tag address. A determination of if the data associated with the received tag address is contained in the cache memory may be made the control circuit, and the control circuit may update and store state information in the dual-port memory responsive to the determination.

Abstract translation: 公开了一种用于处理计算系统中的缓存请求的装置。 该装置可以包括单端口存储器，双端口存储器和控制电路。 单端口存储器可以是与高速缓冲存储器相关联的存储标签信息，并且双端口存储器可以被配置为存储与高速缓冲存储器相关联的状态信息。 控制电路可以被配置为根据接收的标签地址分别接收包括标签地址，访问标签和分别存储在单端口存储器中的状态信息和双端口存储器的请求。 可以确定与接收的标签地址相关联的数据是否包含在高速缓存存储器中，并且控制电路可以响应于该确定来更新和存储双端口存储器中的状态信息。