公开(公告)号：US09823688B2

公开(公告)日：2017-11-21

申请号：US14681599

申请日：2015-04-08

Applicant: Apple Inc.

Inventor： Karthik Rajagopal ,  Narayanan V. Thondugulam ,  Rahul Sharma

IPC: G06F17/50 ,  G06F1/10

CPC classification number: G06F1/10 ,  G06F17/505 ,  G06F2217/62

Abstract: A method for designing a clock tree is disclosed. In one embodiment, a preliminary clock tree design for an integrated circuit (IC) is processed. The clock tree includes a root node, a number of intermediate levels, and a leaf level that is coupled to a number of clocked circuits. Clock gating circuits are placed at the leaf level of the clock tree, and at least some of the intermediate levels. Processing the preliminary clock tree design includes ensuring that an equal number of clock gating circuits are coupled between each leaf level clock gating circuit and the root node. After processing the preliminary clock tree design, clock tree synthesis is performed by executing a clock tree synthesis tool on a computer system to generate a synthesized clock tree design.

公开(公告)号：US20160299524A1

公开(公告)日：2016-10-13

申请号：US14681599

申请日：2015-04-08

Applicant: Apple Inc.

Inventor： Karthik Rajagopal ,  Narayanan V. Thondugulam ,  Rahul Sharma

IPC: G06F1/10 ,  G06F17/50

CPC classification number: G06F1/10 ,  G06F17/505 ,  G06F2217/62

Abstract: A method for designing a clock tree is disclosed. In one embodiment, a preliminary clock tree design for an integrated circuit (IC) is processed. The clock tree includes a root node, a number of intermediate levels, and a leaf level that is coupled to a number of clocked circuits. Clock gating circuits are placed at the leaf level of the clock tree, and at least some of the intermediate levels. Processing the preliminary clock tree design includes ensuring that an equal number of clock gating circuits are coupled between each leaf level clock gating circuit and the root node. After processing the preliminary clock tree design, clock tree synthesis is performed by executing a clock tree synthesis tool on a computer system to generate a synthesized clock tree design.

Abstract translation: 公开了一种用于设计时钟树的方法。 在一个实施例中，处理集成电路（IC）的初步时钟树设计。 时钟树包括根节点，多个中间电平以及耦合到多个时钟电路的叶电平。 时钟门控电路放置在时钟树的叶级，至少部分中间级。 处理初步时钟树设计包括确保在每个叶级时钟选通电路和根节点之间耦合相等数量的时钟门控电路。 在处理初步时钟树设计之后，通过在计算机系统上执行时钟树合成工具来执行时钟树合成，以产生合成时钟树设计。