公开(公告)号：US11775301B2

公开(公告)日：2023-10-03

申请号：US17644016

申请日：2021-12-13

Applicant: Apple Inc.

Inventor： Ran Aharon Chachick ,  Aditya Kesiraju ,  Andrew J. Beaumont-Smith ,  Jong-Suk Lee

IPC: G06F9/30 ,  G06F9/50 ,  G06F15/80 ,  G06F9/38

CPC classification number: G06F9/30123 ,  G06F9/3009 ,  G06F9/384 ,  G06F9/3877 ,  G06F15/80

Abstract: A coprocessor with register renaming is disclosed. An apparatus includes a plurality of processors and a coprocessor respectively configured to execute processor instructions and coprocessor instructions. The coprocessor receives coprocessor instructions from ones of the processors. The coprocessor includes an array of processing elements and a result register set comprising storage elements respectively distributed within the array of processing elements. For a given member of the array of processing elements, a corresponding storage element is configured to store coprocessor instruction results generated by the given member. The result register set implements a plurality of contexts to store respective coprocessor states corresponding to coprocessor instructions received from different processors. Based on a determination that one of the contexts is inactive, the coprocessor is configured to store coprocessor instruction results corresponding to an active context within storage elements of the result register set corresponding to the inactive context.

公开(公告)号：US20250103338A1

公开(公告)日：2025-03-27

申请号：US18628403

申请日：2024-04-05

Applicant: Apple Inc.

Inventor： Ran Aharon Chachick ,  Rajdeep L. Bhuyar ,  Kanghong Yan

IPC: G06F9/30

Abstract: Techniques are disclosed involving operand management using a fusion buffer. A processor includes operand management circuitry, where the operand management circuitry includes a fusion buffer, and execution circuitry. In one embodiment, the operand management circuitry is configured to detect a first storage instruction operation that is executable to store operand values usable by one or more consumer instruction operations and store the first storage instruction operation in the fusion buffer. In response to detecting a drop condition associated with the first storage instruction operation, the operand management circuitry is configured to remove the first storage instruction operation from the fusion buffer without forwarding the first storage instruction operation for execution. In response to detecting a buffer vacate condition and not detecting the drop condition the operand management circuitry is configured to forward the first storage instruction operation for execution by the execution circuitry.

公开(公告)号：US20250103551A1

公开(公告)日：2025-03-27

申请号：US18628460

申请日：2024-04-05

Applicant: Apple Inc.

Inventor： Kanghong Yan ,  Rajdeep L. Bhuyar ,  Ran Aharon Chachick

IPC: G06F15/80

Abstract: Techniques are disclosed involving interleaving and de-interleaving of operands. An embodiment of an apparatus includes an array storage circuit and a control circuit. The array storage circuit is configured to store elements of an array having a plurality of rows and a plurality of columns. The control circuit is configured to write multiple input vectors to the array storage circuit such that elements of a given input vector are split among multiple columns of the plurality of columns and a given row of the plurality of rows has interleaved elements of the multiple input vectors. The control circuit is further configured to output data corresponding to rows of the array to form one or more result values.

公开(公告)号：US20240045680A1

公开(公告)日：2024-02-08

申请号：US18453010

申请日：2023-08-21

Applicant: Apple Inc.

Inventor： Ran Aharon Chachick ,  Aditya Kesiraju ,  Andrew J. Beaumont-Smith ,  Jong-Suk Lee

IPC: G06F9/30 ,  G06F15/80 ,  G06F9/38

CPC classification number: G06F9/30123 ,  G06F15/80 ,  G06F9/3877 ,  G06F9/384 ,  G06F9/3009

Abstract: A coprocessor with register renaming is disclosed. An apparatus includes a plurality of processors and a coprocessor respectively configured to execute processor instructions and coprocessor instructions. The coprocessor receives coprocessor instructions from ones of the processors. The coprocessor includes an array of processing elements and a result register set comprising storage elements respectively distributed within the array of processing elements. For a given member of the array of processing elements, a corresponding storage element is configured to store coprocessor instruction results generated by the given member. The result register set implements a plurality of contexts to store respective coprocessor states corresponding to coprocessor instructions received from different processors. Based on a determination that one of the contexts is inactive, the coprocessor is configured to store coprocessor instruction results corresponding to an active context within storage elements of the result register set corresponding to the inactive context.

公开(公告)号：US20230095072A1

公开(公告)日：2023-03-30

申请号：US17644016

申请日：2021-12-13

Applicant: Apple Inc.

Inventor： Ran Aharon Chachick ,  Aditya Kesiraju ,  Andrew J. Beaumont-Smith ,  Jong-Suk Lee

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/80

Abstract: A coprocessor with register renaming is disclosed. An apparatus includes a plurality of processors and a coprocessor respectively configured to execute processor instructions and coprocessor instructions. The coprocessor receives coprocessor instructions from ones of the processors. The coprocessor includes an array of processing elements and a result register set comprising storage elements respectively distributed within the array of processing elements. For a given member of the array of processing elements, a corresponding storage element is configured to store coprocessor instruction results generated by the given member. The result register set implements a plurality of contexts to store respective coprocessor states corresponding to coprocessor instructions received from different processors. Based on a determination that one of the contexts is inactive, the coprocessor is configured to store coprocessor instruction results corresponding to an active context within storage elements of the result register set corresponding to the inactive context.