公开(公告)号：US20250095098A1

公开(公告)日：2025-03-20

申请号：US18524729

申请日：2023-11-30

Applicant: Apple Inc.

Inventor： Ali Rabbani Rankouhi ,  Roman Tereshin ,  Luca O. Iuliano ,  Sheenam Jayaswal ,  Rohit Kumar Singh

IPC: G06T1/20 ,  G06F9/48 ,  G06F9/50 ,  G06T15/00

Abstract: Techniques are disclosed relating to graphics processor that support ray tracing. In particular, shader circuitry may be configured to adjust a scheduling priority of a single-instruction multiple-data (SIMD) group of a shader program based on a hint that the SIMD group has an upcoming ray intersect command for ray intersect accelerator circuitry and based on a resource usage indication from the ray intersect accelerator circuitry. This may advantageously reduce cache thrashing, e.g., when shaders may allocate memory for ray intersect commands and fill a shared cache faster than the ray intersect accelerator circuitry can process the rays.