公开(公告)号：US09817664B2

公开(公告)日：2017-11-14

申请号：US14625956

申请日：2015-02-19

Applicant: Apple Inc.

Inventor： Shachar Ron ,  Bernard J. Semeria

IPC: G06F9/30

CPC classification number: G06F9/30098 ,  G06F9/30123 ,  G06F9/3851

Abstract: Techniques are disclosed relating to register caching techniques for thread switches. In one embodiment, an apparatus includes a register file and caching circuitry. In this embodiment, the register file includes a plurality of registers and the caching circuitry is configured to store information that indicates threads that correspond to data stored in respective ones of the plurality of registers. In this embodiment, the apparatus is configured to store, at a point in time at which a first register of the plurality of registers includes first valid data corresponding to a first thread, second valid data corresponding to a second thread in a second register of the plurality of registers. In some embodiments, the disclosed techniques may reduce context switch latency, reduce pressure on a data cache, and/or allow smaller slices of thread execution, for example.

公开(公告)号：US20160246728A1

公开(公告)日：2016-08-25

申请号：US14625956

申请日：2015-02-19

Applicant: Apple Inc.

Inventor： Shachar Ron ,  Bernard J. Semeria

IPC: G06F12/08 ,  G06F9/30

CPC classification number: G06F9/30098 ,  G06F9/30123 ,  G06F9/3851

Abstract: Techniques are disclosed relating to register caching techniques for thread switches. In one embodiment, an apparatus includes a register file and caching circuitry. In this embodiment, the register file includes a plurality of registers and the caching circuitry is configured to store information that indicates threads that correspond to data stored in respective ones of the plurality of registers. In this embodiment, the apparatus is configured to store, at a point in time at which a first register of the plurality of registers includes first valid data corresponding to a first thread, second valid data corresponding to a second thread in a second register of the plurality of registers. In some embodiments, the disclosed techniques may reduce context switch latency, reduce pressure on a data cache, and/or allow smaller slices of thread execution, for example.

Abstract translation: 公开了关于线程开关的寄存器缓存技术的技术。 在一个实施例中，装置包括寄存器文件和高速缓存电路。 在该实施例中，寄存器文件包括多个寄存器，并且高速缓存电路被配置为存储指示对应于存储在多个寄存器的相应数据中的数据的线程的信息。 在本实施例中，该装置被配置为在多个寄存器中的第一寄存器包括与第一线程相对应的第一有效数据的时间点存储对应于第一线程的第二寄存器中的第二线程的第二有效数据 多个寄存器。 在一些实施例中，例如，所公开的技术可以减少上下文切换等待时间，减少数据高速缓存上的压力和/或允许更小的线程执行。