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    Unified addressable memory
    1.
    发明授权
    Unified addressable memory 有权

    公开(公告)号：US11138346B2

    公开(公告)日：2021-10-05

    申请号：US16859634

    申请日：2020-04-27

    Applicant: Apple Inc.

    Inventor： Manu Gulati ,  Joseph Sokol, Jr. ,  Jeffrey R. Wilcox ,  Bernard J. Semeria ,  Michael J. Smith

    IPC: G06F21/72 ,  G06F12/02 ,  G06F12/1027 ,  G06F12/14 ,  G06F21/78 ,  H04L9/08

    Abstract: In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.

    Unified addressable memory
    3.
    发明授权
    Unified addressable memory 审中-公开

    公开(公告)号：US10671762B2

    公开(公告)日：2020-06-02

    申请号：US15748893

    申请日：2016-08-25

    Applicant: Apple Inc.

    Inventor： Manu Gulati ,  Joseph Sokol, Jr. ,  Jeffrey R. Wilcox ,  Bernard J. Semeria ,  Michael J. Smith

    IPC: G06F21/72 ,  G06F12/02 ,  G06F12/1027 ,  G06F12/14 ,  G06F21/78 ,  H04L9/08

    Abstract: In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.

    Page Protection Layer
    4.
    发明申请
    Page Protection Layer 审中-公开

    公开(公告)号：US20200081847A1

    公开(公告)日：2020-03-12

    申请号：US16564502

    申请日：2019-09-09

    Applicant: Apple Inc.

    Inventor： Julien Oster ,  Thomas G. Holland ,  Bernard J. Semeria ,  Jason A. Harmening ,  Pierre-Olivier J. Martel ,  Gregory D. Hughes ,  P. Love Hornquist Astrand ,  Jacques Fortier ,  Ryan P. Nielson ,  Simon P. Cooper

    IPC: G06F12/1009 ,  G06F21/62 ,  G06F9/455

    Abstract: In an embodiment, a computer system comprises a page protection layer. The page protection layer may be the component in the system which manages the page tables for virtual to physical page mappings. Transactions to the page protection layer are used to create/manage mappings created in the page tables. The page protection layer may enforce dynamic security policies in the system (i.e. security policies that may not be enforced using only a static hardware configuration). In an embodiment, the page protection layer may ensure that it is the only component which is able to modify the page tables. The page protection layer may ensure than no component in the system is able to modify a page that is marked executable in any process' address space. The page protection may ensure that any page that is marked executable has code with a verified code signature, in an embodiment.

    PC-Based Memory Permissions
    5.
    发明公开
    PC-Based Memory Permissions 审中-公开

    公开(公告)号：US20230418767A1

    公开(公告)日：2023-12-28

    申请号：US18343125

    申请日：2023-06-28

    Applicant: Apple Inc.

    Inventor： Jeffry E. Gonion ,  Bernard J. Semeria

    IPC: G06F12/14 ,  G06F12/1027

    CPC classification number: G06F12/1483 ,  G06F12/1027 ,  G06F12/1475

    Abstract: A memory permissions model for a processor that is based on the memory address accessed by an instruction as well as the program counter of the instruction. These permissions may be stored in permissions tables and indexed using the memory addresses of the instruction and the address of the memory locations that it accesses. Those indexes may be obtained from a page table in some cases. These memory permissions may be used in conjunction with other permissions, such as execute permissions and secondary execution privileges that are based on whether the instruction belongs to a particular instruction group.

    PC-based instruction group permissions
    9.
    发明授权
    PC-based instruction group permissions 有权

    公开(公告)号：US12079142B2

    公开(公告)日：2024-09-03

    申请号：US18343145

    申请日：2023-06-28

    Applicant: Apple Inc.

    Inventor： Jeffry E. Gonion ,  Bernard J. Semeria

    IPC: G06F9/30 ,  G06F12/1027 ,  G06F12/14 ,  G06F21/52

    CPC classification number: G06F12/1483 ,  G06F9/30076 ,  G06F9/30189 ,  G06F12/1027 ,  G06F12/1475 ,  G06F21/52 ,  G06F2221/034

    Abstract: A permissions model for a processor in which permissions are based on the instruction group of an instruction. These permissions may be stored in permissions tables and indexed using the program counter of the instruction. The permissions may identify which of a plurality of instruction groups of an instruction set architecture (ISA) of a processor are permitted to execute from that program counter value. Accordingly, the instruction group of the instruction can be compared to the permitted instruction groups to determine if the instruction has execution permission. In some cases, the instruction-group-based permissions are secondary execution privileges; additional primary execution permissions that are determined using the program counter may also be used.

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