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    CAPACITANCE MEASUREMENT CIRCUIT
    1.
    发明申请
    CAPACITANCE MEASUREMENT CIRCUIT 审中-公开
    电容测量电路

    公开(公告)号：US20140009176A1

    公开(公告)日：2014-01-09

    申请号：US13691285

    申请日：2012-11-30

    Applicant: APPLE INC.

    Inventor： Saman Saeedi ,  Shafiq M. Jamal ,  Ahmad AI-Dahle

    IPC: G01R27/26

    CPC classification number: G01R27/2605 ,  G09G3/006 ,  G09G3/3648 ,  G09G2320/043

    Abstract: A resistor having a known resistance is coupled in series with a device under test (DUT) having an unknown capacitance. An ac signal source having a known fundamental frequency is coupled to drive the resistor to thereby produce a first ac signal. A phase controllable signal generator produces a second ac signal. The first and second ac signals are fed to a mixer. An output of the mixer is low pass filtered. A peak detector monitors the low pass filtered output while sweeping the phase controllable signal generator, until a peak is detected. The set phase corresponding to the detected peak is then used to obtain an estimate of the unknown DUT capacitance. Other embodiments are also described and claimed.

    Abstract translation: 具有已知电阻的电阻器与具有未知电容的被测器件（DUT）串联耦合。 具有已知基频的交流信号源被耦合以驱动电阻器从而产生第一交流信号。 相位可控信号发生器产生第二交流信号。 第一和第二交流信号被馈送到混频器。 混频器的输出被低通滤波。 峰值检测器在扫描相位可控信号发生器时监视低通滤波输出，直到检测到峰值。 然后使用与检测到的峰对应的设定相位来获得未知DUT电容的估计。 还描述和要求保护其他实施例。

    PIXEL LEAKAGE COMPENSATION
    2.
    发明申请
    PIXEL LEAKAGE COMPENSATION 审中-公开
    像素泄漏补偿

    公开(公告)号：US20130321378A1

    公开(公告)日：2013-12-05

    申请号：US13661404

    申请日：2012-10-26

    Applicant: APPLE INC.

    Inventor： Shafiq M. Jamal ,  Yafei Bi

    IPC: G09G5/00

    CPC classification number: G09G3/3648 ,  G09G3/006 ,  G09G2320/0204 ,  G09G2330/12

    Abstract: A display system has a display panel in which there are a first subset of pixels and a second subset of pixels. A first common voltage generation circuit drives a first common voltage line that is coupled to the first subset, and a second common voltage generation circuit drives a second common voltage line that is coupled to the second subset. A difference circuit has an input coupled to a first node of a pixel in the first subset, and a further input coupled to a first node of a pixel in the second subset. The difference circuit generates a sensed pixel signal difference. The second common voltage generation uses the sensed difference to compensate for pixel leakage differences between the pixels of the first and second subsets. Other embodiments are also described and claimed.

    Abstract translation: 显示系统具有显示面板，其中存在像素的第一子集和像素的第二子集。 第一公共电压产生电路驱动耦合到第一子集的第一公共电压线，第二公共电压产生电路驱动耦合到第二子集的第二公共电压线。 差分电路具有耦合到第一子集中的像素的第一节点的输入，以及耦合到第二子集中的像素的第一节点的另一输入。 差分电路产生检测到的像素信号差。 第二公共电压产生使用感测到的差异来补偿第一和第二子集的像素之间的像素泄漏差异。 还描述和要求保护其他实施例。

    TESTING OF INTEGRATED CIRCUIT TO SUBSTRATE JOINTS
    5.
    发明申请
    TESTING OF INTEGRATED CIRCUIT TO SUBSTRATE JOINTS 有权
    集成电路测试接地

    公开(公告)号：US20140125645A1

    公开(公告)日：2014-05-08

    申请号：US13710884

    申请日：2012-12-11

    Applicant: APPLE INC.

    Inventor： Mir B. Ghaderi ,  Shafiq M. Jamal ,  Sang Y. Youn

    IPC: G09G3/36

    CPC classification number: G09G3/006

    Abstract: A method for testing integrated circuit-to-substrate joints that electrically connect an IC to a substrate. An ammeter is coupled to a test node of the driver IC, while the test node is coupled to a current source, and a measured current output of the ammeter is recorded. A voltmeter is coupled to the test node while the test node is coupled to an end node of a group of dummy IC-to-substrate joints that are daisy chained; a first measured voltage output of the voltmeter is then recorded. The IC then couples the test node to another end node of the daisy chained dummy joints, and a second measured voltage output is recorded. A resistance or admittance value for the electrical connection of the IC to the substrate is then computed, using the first and second measured voltage outputs and the measured current output. Other embodiments are also described and claimed.

    Abstract translation: 一种用于测试将IC电连接到衬底的集成电路到衬底接头的方法。 电流表耦合到驱动器IC的测试节点，而测试节点耦合到电流源，并记录电流表的测量电流输出。 电压表耦合到测试节点，而测试节点耦合到菊花链的一组虚拟IC到衬底接头的端节点; 然后记录电压表的第一测量电压输出。 然后，IC将测试节点耦合到菊花链虚拟接头的另一端节点，并记录第二测量电压输出。 然后使用第一和第二测量电压输出和测量的电流输出来计算IC与衬底的电连接的电阻或导纳值。 还描述和要求保护其他实施例。

    Testing of integrated circuit to substrate joints
    6.
    发明授权
    Testing of integrated circuit to substrate joints 有权
    集成电路到基板接头的测试

    公开(公告)号：US09472131B2

    公开(公告)日：2016-10-18

    申请号：US13710884

    申请日：2012-12-11

    Applicant: Apple Inc.

    Inventor： Mir B. Ghaderi ,  Shafiq M. Jamal ,  Sang Y. Youn

    IPC: G09G3/00

    CPC classification number: G09G3/006

    Abstract: A method for testing integrated circuit-to-substrate joints that electrically connect an IC to a substrate. An ammeter is coupled to a test node of the driver IC, while the test node is coupled to a current source, and a measured current output of the ammeter is recorded. A voltmeter is coupled to the test node while the test node is coupled to an end node of a group of dummy IC-to-substrate joints that are daisy chained; a first measured voltage output of the voltmeter is then recorded. The IC then couples the test node to another end node of the daisy chained dummy joints, and a second measured voltage output is recorded. A resistance or admittance value for the electrical connection of the IC to the substrate is then computed, using the first and second measured voltage outputs and the measured current output. Other embodiments are also described and claimed.

    Abstract translation: 一种用于测试将IC电连接到衬底的集成电路到衬底接头的方法。 电流表耦合到驱动器IC的测试节点，而测试节点耦合到电流源，并记录电流表的测量电流输出。 电压表耦合到测试节点，而测试节点耦合到菊花链的一组虚拟IC到衬底接头的端节点; 然后记录电压表的第一测量电压输出。 然后，IC将测试节点耦合到菊花链虚拟接头的另一端节点，并记录第二测量电压输出。 然后使用第一和第二测量电压输出和测量的电流输出来计算IC与衬底的电连接的电阻或导纳值。 还描述和要求保护其他实施例。

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