公开(公告)号：US20170366170A1

公开(公告)日：2017-12-21

申请号：US15355109

申请日：2016-11-18

Applicant: Apple Inc.

Inventor： Zhao Wang ,  Sheela R. Shreedharan ,  Ajay Kumar Bhatia ,  Michael R. Seningen

IPC: H03K3/012 ,  H03K3/3562

CPC classification number: H03K3/012 ,  H03K3/35625

Abstract: An apparatus includes a master latch circuit including a first circuit and a second circuit, and a slave latch circuit including a third circuit and a fourth circuit. The first circuit and the second circuit may be coupled to a first shared circuit node, and the third circuit and the fourth circuit may be coupled to a second shared circuit node. The master latch circuit may be configured to store a value of an input signal in response to an assertion of a clock signal. The slave latch circuit may be configured to store an output value of the master latch circuit in response to a de-assertion of the clock signal. The master latch circuit may also be configured to de-couple the first shared circuit node from a ground reference node in response to the de-assertion of the clock signal.

公开(公告)号：US10033356B2

公开(公告)日：2018-07-24

申请号：US15355109

申请日：2016-11-18

Applicant: Apple Inc.

Inventor： Zhao Wang ,  Sheela R. Shreedharan ,  Ajay Kumar Bhatia ,  Michael R. Seningen

IPC: H03K3/012 ,  H03K3/3562

Abstract: An apparatus includes a master latch circuit including a first circuit and a second circuit, and a slave latch circuit including a third circuit and a fourth circuit. The first circuit and the second circuit may be coupled to a first shared circuit node, and the third circuit and the fourth circuit may be coupled to a second shared circuit node. The master latch circuit may be configured to store a value of an input signal in response to an assertion of a clock signal. The slave latch circuit may be configured to store an output value of the master latch circuit in response to a de-assertion of the clock signal. The master latch circuit may also be configured to de-couple the first shared circuit node from a ground reference node in response to the de-assertion of the clock signal.